Nvidia Corporation

Sing-Rong Li

Lei Wang

Hwong-Kwo Lin

Haiyan Gong

Pai-Yi Chang

A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

Write assist negative bit line voltage generator for SRAM array

A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.

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Sing-Rong Li