Taiwan Semiconductor Manufacturing Comp. Ltd.

Sing-Kai Huang

Jack Liu

Charles Chew-Yuen Young

Jiann-Tyng Tzeng

Chih-Liang Chen

Wei-Cheng Wu

Ching-Fang Huang

Chew-Yuen Young

Kam-Tou Sio

Yi-Chuin Tsai

Shang-Wei Fang

An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.

Integrated circuit with mixed row heights

A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.

Method of manufacturing a semiconductor device

Some embodiments relate to a sense amplifier. The sense amplifier includes a fully-depleted silicon on insulator (FDSOI) substrate, including a handle substrate region, an insulator layer over the handle substrate region, and a device region over the insulator layer. An n-well region is disposed in the handle substrate region, and an n-well contact region extends from the n-well region through the insulator layer to an upper surface of the device region. A pair of pull-down transistors are disposed in the device region and over the n-well. The pair of pull-down transistors have their respective gates coupled to a pair of complementary bitlines, respectively, and coupled to the n-well through the n-well contact region.

FDSOI sense amplifier configuration in a memory device

A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.

A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.

Growing community of inventors

Yunlin County, Taiwan

Sing-Kai Huang