Actel Corporation, Inc.

Altera Corporation

Microsemi Soc Corporation

Acatel

Sinan Kaptanoglu

Bruce B Pedersen

David Lewis

Andy Louie Lee

James G Schleicher

King W Chan

William C Plants

Gregg William Baeckler

Henry Kim

Richard Yuan

Rahul Saini

Michael David Hutton

Jung-Cheun Lien

Mike Hutton

David Wolk Mendel

Wenyi Feng

Gregory William Bakker

Marko Chew

Runip Gopisetty

Jinyong Yuan

Chi Fung Cheng

Tim Michael Vanderhoek

Samuel W Beal

Khaled A El Ayat

William Shu

Khaled A El-Avat

Jonathan W Greene

Abbas A El Gamal

Khaled A El-Ayat

James G Schleicher, Ii

William C T Shu

Joel D Landry

Warren K Miller

John E McGowan

Johathan W Greene

Khaled A ElAyat

Bruce B Pedersén

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.

Apparatus and methods for time-multiplex field-programmable gate arrays

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Dedicated interface architecture for a hybrid integrated circuit

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Omnibus logic element for packing or fracturing

An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Enhanced field programmable gate array

A multiple-clock time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry. A plurality of clock signals within the TM-FPGA couple to the programmable logic circuitry. A user's circuit can be mapped to the programmable logic circuitry without the user's intervention in mapping the circuit to the programmable logic circuitry.

Apparatus and methods for time-multiplex field-programmable gate arrays with multiple clocks

A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Fracturable lookup table and logic element

A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Dedicated crossbar and barrel shifter block on programmable logic resources

A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

(N+1) input flip-flop packing with logic in FPGA architectures

Growing community of inventors

Belmont, CA, United States of America

Sinan Kaptanoglu