Qualcomm Incorporated

Sina Dena

Bohuslav Rychlik

Rahul Gulati

Jaya Prakash Subramaniam Ganasan

Dipti Ranjan Pal

Jason Edward Podaima

Steven Halter

Paul Christopher John Wiercienski

Bipin Duggal

Amod Phadke

Manokanthan Somasundaram

Vanamali Bhat

Myil Ramkumar

Christophe Denis Bernard Avoinne

Federico Salluzzo

Steven John Halter

An apparatus including a serial clock routing pipeline including a first set of clock inputs and a clock output; a first set of clock generators including a first set of clock outputs coupled to the first set of clock inputs of the serial clock routing pipeline, respectively; and a first clock monitoring unit including a first clock input coupled to the clock output of the serial clock routing pipeline, and a first status output to provide information concerning one or more of the first set of clock generators. The apparatus may further include a set of phase locked loops (PLLs) coupled to the set of clock generators, respectively; the set of PLLs also coupled to the clock monitoring unit.

Clock monitoring unit with serial clock routing pipeline

In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

On-chip frequency monitoring

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

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San Diego, CA, United States of America

Sina Dena