Samsung Electronics Co., Ltd.

Sin-jin Kim

Ho-Sun Chung

Tae-hun Kim

Disclosed is a multi-layer neural network and circuit design method. The multi-layer neural network receiving an m-bit input and generating an n-bit output comprises a neuron having a cascaded pair of CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as its inverted output node and an output node of the succeeding CMOS inverter as its non-inverted output node, an input layer having m neurons to receive the m-bit input, an output layer having n neurons to generate the n-bit output, at least one hidden layer provided with n neurons to transfer the input received from the input layer to the directly upper hidden layer or the output layer, an input synapse group in a matrix having each predetermined weight value to connect each output of neurons on the input layer to each neuron of the output layer and at least one hidden layer, at least one transfer synapse group in a matrix having each predetermined weight value to connect each output of neurons of the hidden layer to each neuron of its directly upper hidden layer or of the output layer, and a bias synapse group for biasing each input node of neurons of the hidden layers and the output layer.

MOS Multi-layer neural network and its design method

A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.

Divider using neural network

A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.

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Taegu, South Korea

Sin-jin Kim