Hitachi, Ltd.

Sin-ichi Sinoda

Masahiro Iwamura

Kazuo Kato

Hideo Maejima

Takashi Hotta

Yasuhiro Nakatsuka

Tadaaki Bandoh

Shigeya Tanaka

Kozaburo Kurita

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K , And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K .

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Information processor and information processing system utilizing clock

Data processing system generating clock signal from an input clock,

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

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Hitachi, Japan

Sin-ichi Sinoda