Texas Instruments Corporation

Simonjit Dutta

Timothy David Anderson

Jonathan H Shiell

Ashwini K Nanda

James O Bondi

A microprocessor with an execution stage (,) including a plurality of execution units and an instruction memory (,) for storing instructions. The microprocessor further includes circuitry for retrieving (,) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (,) for storing a plurality of information fields (,) corresponding to a branch instruction. The information fields include at least a target instruction address (T,), a prediction field (P,) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPA,) indicating accuracy for past prediction fields. In operation, the circuitry for retrieving instructions retrieves (,), as a next instruction to follow the branch instruction, an instruction corresponding to the target instruction address in response to a function (TP,) responsive to the accuracy measure exceeding a predetermined threshold and the prediction field indicating program flow should pass to the target instruction address. Additionally, the circuitry for retrieving instructions retrieves (,), in response to the function responsive to the accuracy measure not exceeding a predetermined threshold, a first group of instructions, wherein the first group of instructions is sequentially arranged after the branching branch instruction and includes an instruction corresponding to the target instruction address.

Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy

A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit. The output of the multiplexer is coupled to an input of a second stage (50) of the intermediary stages, wherein the second stage follows the first stage. Other circuits, systems, and methods are also disclosed and claimed.

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Dallas, TX, United States of America

Simonjit Dutta