Stmicroelectronics S.r.l.

Novellus Systems Incorporated

Sgs-thomson Microelectronics S.r.l.

Simone Alba

Yuh-Jia (Jim) Su

David L Chen

Senzi Li

Simona Petroni

Giuseppe Colangelo

Eddie Ka Ho Chiu

Maria Paola Pozzoli

Emilio Giambattista Ghio

Omar Vassalli

Andrea Colognese

Roberto Colombo

Enrico Bellandi

Barbara Zanderighi

Alessandro Spandre

Carmelo Romeo

Francesco Ciovacco

Francesca Canali

Claudio Savoia

Francedillaois Maugain

Giovanni Rivera

Chiara Savardi

The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

Method for post-etch cleans

The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

Methods for post etch cleans

The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Method for reducing defects after a metal etching in semiconductor devices

A method for defining geometries in a semiconductor wafer supported on a plate electrode in a processing chamber includes forming a reusable refractory coated laminar mask. The reusable refractory coated laminar mask is formed by defining the geometries in a laminar mask substrate, forming apertures through the laminar mask substrate, and forming a layer of refractory material over at least one surface of the laminar mask substrate. The reusable refractory coated laminar mask is positioned over the semiconductor wafer. Treating of the semiconductor wafer is performed through the apertures of the reusable refractory coated laminar mask. The treating may be plasma etching or ion etching.

Nonlithographic method of defining geometries for plasma and/or ion implantation treatments on a semiconductor wafer

A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Method for manufacturing electronic circuits integrated on a semiconductor substrate

The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the layer to be etched. The masking layer is made so as to be conductive, at least during one part of the etching step; in this way, the electrons implanted on the top part of the masking layer during plasma etching can recombine with the positive charges which have reached the layer to be etched. The recombination of the charges makes it possible to prevent damage from plasma resulting from the formation of parasitic electric currents which are detrimental to the electronic device itself.

Process for the fabrication of integrated devices with reduction of damage from plasma

A method enhances selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of fabrication processes of an electronic semiconductor device starting from a semiconductor material wafer. The method includes radiating the wafer with an ion beam subsequently to depositing the layer to be etched and defining a circuit pattern on the film of light-sensitive material. An alternative method exposes the wafer to a non-reactive gas medium under plasma rather than radiating the wafer with an ion beam.

Method for enhancing selectivity between a film of a light-sensitive material and a layer to be etched in electronic semiconductor device fabrication processes

Method of measuring the thickness of a layer of silicon damaged by plasma etching

A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

Method for assessing the effects of plasma treatments on wafers of

The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

Growing community of inventors

Milan, Italy

Simone Alba