International Business Machines Corporation

Simon Weishaupt

Timothy John Slegel

Matthias Klein

Mark S Farrell

Bruce C Giamei

Anthony Thomas Sofia

Jonathan D Bradbury

Anthony Saporito

Cedric Lichtenau

Ashutosh Misra

Girish Gopala Kurup

Timothy J Siegel

Mahmoud Amin

Ashutosh Mishra

Laith M AlBarakat

Christian Jacobi

Louis P Gomes

Bernd Nerz

Wolfgang Fischer

Stefan Usenbinz

Holger Horbach

Puja Sethia

Bruce Conrad Giamei

Instruction processing is performed for an instruction. The instruction is configured to perform a function, which is to be performed in a plurality of processing phases. A processing phase is defined to store up to a selected amount of data. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of the function. Based on determining that the store into the designated area occurred, an interrupt is presented.

Program event recording storage alteration processing for a neural network accelerator instruction

A computer system configured to perform operations for validating memory access patterns of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on memory access patterns and storing memory accesses in a first table, and executing the static variant of the program instruction stream on the accelerator processing unit. During execution, the virtual addresses may be discarded and replaced by the addresses provided in the address translation list. The operations may include recording and storing every memory access of executing the static variant of the program instruction stream in a second table and comparing the memory access patterns stored in the second table to memory accesses patterns stored in the first table. Memory access patterns may be validated or discarded.

Validating memory access patterns of static program code

Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

An instruction is executed to perform a query function. The executing includes obtaining information relating to a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

Instruction to query for model-dependent information

A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

Neural network processing assist instruction

A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.

Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment

A processor requests that a data transformation operation be performed using another processor, in which the data transformation operation is performed asynchronously. A determination is made that the data transformation operation performed using the other processor has completed unsatisfactorily, and based on the unsatisfactory completion, status relating to performance of the data transformation operation is incomplete. The data transformation operation is then re-executed synchronously using the one processor, and the re-executing provides status information unavailable in performing the data transformation operation asynchronously.

Synchronous re-execution of a data transformation operation to obtain further details regarding an exception

An approach for providing exclusive access to a resource shared by a plurality of processes in a computer system. The approach includes a computer processor retrieving a process identifier for a first process attempting to access the resource, where the process identifier is uniquely assigned to each process of the plurality of processes requiring the resource with the computer system. The approach includes the computer processor using the process identifier for the first process and a mutual exclusion object that includes a lock position allowing exclusive access to the resource and a wait position for a next process to attain the lock position to provide exclusive access to the resource.

Self-managed lock access

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

Verifying the correctness of a deflate compression accelerator

An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data

A system architecture is provided and includes first and second processing units respectively communicative with an on-chip coherency unit and an accelerator communicative with the on-chip coherency unit. The accelerator is configured to execute an operation responsive to a call issued by one of the first and second processing units. The first processing unit is configured to set an asynchronous operation flag (AOF) to indicate that the second processing unit is to conduct an operation for the first processing unit. The second processing unit is configured to respond to the AOF by building scatter gather lists and subsequently issuing the call and feeding the scatter gather lists to the accelerator to facilitate execution of the operation by the accelerator.

Secure and efficient application data processing

A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general-purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performed by the instruction being a compression function or a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.

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Stuttgart, Germany

Simon Weishaupt