Taiwan Semiconductor Manufacturing Comp. Ltd.

Simon Su-Horng Lin

Chin-Hsiang Lin

Chi-Ming Yang

Chyi Shyuan Chern

Chyi-Shyuan Chern

Shao-Yen Ku

Yu-Ming Lee

A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.

Integration of bottom-up metal film deposition

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

N/P metal crystal orientation for high-K metal gate Vt modulation

A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than &#x2212;1.4 volts.

Growing community of inventors

Hsinchu, Taiwan

Simon Su-Horng Lin