Nvidia Corporation

Hong Kong Applied Science and Technology Research Institute Company, Limited

Simon S Moy

John Erik Lindholm

David B Kirk

John Stephen Montrym

Paolo Enrique Sabella

Kevin Dawallu

Matthew Nicholas Papakipos

Douglas A Voorhies

Nicholas J Foskett

Mingjian Yang

Henry Packard Moreton

Brett Coon

John R Nickolls

Emmett Michael Kilgariff

Sean Jeffrey Treichler

John M Danskin

Bryon S Nordquist

Robert Steven Glanville

Svetoslav D Tzvetkov

Ming Yiu Siu

Cass Watson Everitt

Samuel Kan Liu

Roger L Allen

Thomas H Kong

Pao Sabella

Wing Yee Lo

Brett W Coon

A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

System, method and article of manufacture for a programmable processing model with instruction set

Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.

Hierarchical processor array

Resources to be used by concurrent threads in a multithreaded processor are allocated based on thread types of the threads. For each of at least two thread types, an amount of the resource is reserved, and amounts currently allocated are tracked. When a request to allocate some of the resource to a new thread is received, a determination as to whether the allocation can be made is based on the thread type of the new thread, the amount of the resource reserved for that thread type, and the amount currently allocated to threads of that type.

Thread-type-based resource allocation in a multithreaded processor

Resources to be used by concurrent threads in a multithreaded processor are allocated based on thread types of the threads, and thread-type-based criteria governing resource allocation decisions are dynamically modified based on feedback information indicating the degree to which various thread types are using the resource. For each of at least two thread types, an amount of the resource is reserved, and amounts currently allocated are tracked. When an allocation request for a new thread is received, the allocation is made or not based on the new thread's type, the amount of the resource reserved for that type, and the amount currently allocated to threads of that type. If, based on feedback information from the allocation decision, the amount of the resource reserved for one thread type is determined to be insufficient, the reserved amounts are modified to better meet the demand.

Thread-type-based load balancing in a multithreaded processor

Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Constant versioning for multi-threaded processing

A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Register based queuing for texture requests

A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.

System, method and computer program product for branching during programmable vertex processing

Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.

Across-thread out-of-order instruction dispatch in a multithreaded microprocessor

Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of processing elements (PEs) and to perform instruction variances by the PEs. A CSIMD instruction is received, comprising a command and an index to the lookup table (LUT), to be executed by the PEs. The command of the received CSIMD instruction is executed in parallel differently by the PEs using the LUT index to randomly access the memory locations.

Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit

An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.

Growing community of inventors

Los Altos, CA, United States of America

Simon S Moy