Intel Corporation

Micron Technology Incorporated

Simon Ramage

Aliasgar S Madraswala

Naveen Vittal Prabhu

Curtis A Gittens

Scott Nelson

David B Carlton

Donia Sebastian

Kai-Uwe Schmidt

Richard Paul Mangold

Andrew Warrack Morning-Smith

Sowmiya Jayachandran

Zeljko Zupanc

Jason A Gayman

Joerg Hartung

Mary Goodman

Alice Allen

Justin Elkow

A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

Fault tolerance for power loss imminent circuitry failure

Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

NAND flash thermal alerting

In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

Power management and monitoring for storage devices

A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool. The method may further include releasing the one or more credits to the memory channel. The one or more released credits are used to perform the memory operation.

Mechanism for facilitating power and performance management of non-volatile memory in computing devices

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Vancouver, Canada

Simon Ramage