Qualcomm Incorporated

Simon Peter William Booth

Wesley James Holland

Huang Huang

Bohuslav Rychlik

George Patsilaras

Mehrad Tavakoli

Injoon Hong

Jeffrey Shabel

Gerhard Reitmayr

Andrew Edmund Turner

Subbarao Palacharla

Hiral Nandu

Matthew Levi Severson

Meghal Varia

Alain Artieri

Rashmi Kulkarni

Girish Bhat

Jason Edward Podaima

Steven Halter

Kyle Ernewein

Paul Christopher John Wiercienski

Kedar Bhole

Carlos Javier Moreira

Songhe Cai

Cristian Duroiu

Ling Feng Huang

Satish Anand

Alexander Miretsky

Vipul Gandhi

Chih-Chi Cheng

Ruolong Liu

Rakesh Raju Chenna Madhavuni

Younghoon Kim

Serag Monier GadelRab

Yen-Kuan Wu

Rakesh Kumar Gupta

Thomas David Dryburgh

Kangmin Lee

Kyle John Ernewein

Serag Monier Gadelrab

Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

Physical address based set partitioning

Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Pose estimation in extended reality systems

Aspects presented herein relate to methods, devices, and apparatuses for display processing. The apparatus may obtain a first intensity map associated with first luminance information for a scene. The apparatus may also configure a second intensity map based on the first intensity map and at least one coordinate frame from a perspective of a user of a device for display content associated with the scene. The apparatus may also determine whether luminance information for at least one region in the second intensity map is within a suitable luminance range for the display content associated with the scene. The apparatus may also process a set of pixels corresponding to a section in a display associated with the at least one region based on the luminance information being at least one of: within the suitable luminance range, outside of the suitable luminance range, or within an indistinguishable luminance range.

Reprojection optimization based on contextual brightness

Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

Multimedia compressed frame aware cache replacement policy

In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Multi-stage biometric authentication

In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

System state management

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

System and method for intelligent tile-based prefetching of image frames in a system on a chip

Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

Providing memory management functionality using aggregated memory management units (MMUs)

Growing community of inventors

San Diego, CA, United States of America

Simon Peter William Booth