Intel Corporation

Simon N Peffers

Vinodh Gopal

Kirk S Yap

Sean M Gulley

Aaron Gorius

Ned M Smith

Rajesh Poornachandran

Wajdi K Feghali

James D Guilford

Michael T Crocker

Michael J Nolan

Naoki Matsumura

Steven J Lloyd

Sanu K Mathew

Daniel Cutter

Larry R Tate

Thomas L Dmukauskas

In some examples, an apparatus uses a blockchain to agree on a time in an information exchange network. A first node includes a processor communicatively coupled to a storage device including instructions. When executed by the processor, the instructions cause the processor to verify a time estimate from each of one or more other node, to determine a time match of a time estimate of the first node with the time estimates from the one or more other node, and if the time match is determined, to commit to the blockchain a transaction that includes a time stamp.

Protection of information in an information exchange

In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.

Battery charge termination voltage adjustment

Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

Delayed link compression scheme

In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.

System, apparatus and method for dynamic priority-aware compression for interconnect fabrics

Systems and methods for exchanging digital content in an online layered hierarchical market and exchange network are disclosed. A Buyer utilizes one or more Curry functions that are relevant to content to be acquired thereby developing a Margin Future estimate for the received content. Each e-market layer in the hierarchy adds value to the content for use with one or more other e-market layers. Value is added by executing a Margin Function including a Curry function on the content, as defined in the Margin Future. An embodiment includes data, information, knowledge, and wisdom (DIKW) e-market layers. The Margin Future estimate may be recorded with an escrow agent acting as an intermediary with Investors. Once funded, the Buyer may acquire the content from the Seller and apply value added. Payment may be made when the value added content enters the e-market using electronic wallets. Other embodiments are described and claimed.

Hierarchical data information

Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios. The schemes may be implemented to improve the effective bandwidth of various types of links, including serial links, bus-type links, and socket-to-socket links in multi-socket systems.

Low-latency link compression schemes

Data element filter logic ('hardware accelerator') in a processor that offloads computation for an in-memory database select/extract operation from a Central Processing Unit (CPU) core in the processor is provided. The Data element filter logic provides a balanced performance across an entire range of widths (number of bits) of data elements in a column-oriented Database Management System.

Method and apparatus to efficiently perform filter operations for an in-memory relational database

Methods and apparatuses relating to accelerating blockchain transactions are described. In one embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction, and the hardware accelerator includes a dispatcher circuit to route the operation to a transaction processing circuit when the operation is a transaction operation and route the operation to a block processing circuit when the operation is a block operation. In another embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction; and a network interface controller including a dispatcher circuit to route the operation to a transaction processing circuit of the hardware accelerator when the operation is a transaction operation and route the operation to a block processing circuit of the hardware accelerator when the operation is a block operation.

Apparatuses, methods, and systems for blockchain transaction acceleration

Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.

Technologies for big data analytics accelerator

In one embodiment, an apparatus includes: a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit; a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value. Other embodiments are described and claimed.

System, apparatus and method for providing a unique identifier in a fuseless semiconductor device

Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.

Systems and methods for guardband recovery using in situ characterization

Embodiments are generally directed to automatic focus prescription lens eyeglasses. An embodiment of an apparatus includes one or more variable focus lenses coupled; one or more actuators to change the focus of the variable focus lenses; and one or more focus distance components coupled to detect a focus distance of one or more eyes of a user of the apparatus. The one or more actuators set a focal distance of each of the one or more variable focus lenses, a focal distance setting for each of the one or more variable focus lenses being determined in response to the focus distance of the one or both eyes of the user; and the focal distance setting for each of the one or more variable focus lenses includes adjustment for a vision prescription of the user.

Growing community of inventors

Acton, MA, United States of America

Simon N Peffers