Bull Sas

Simon Martiel

Arnaud Gazda

Timothee Goubault De Brugiere

Timothée Goubault De Brugière

Cyril Allouche

Thomas Ayral

Elise Rubat Ciagnus

Jon Oillarburu

A technique for implementing a quantum circuit is provided, where the quantum circuit includes qubits and operators executed on the qubits. The operators include a sequence of π/4 Pauli rotation gates. A surface code layout includes an arrangement of the quantum circuit on a quantum chip, where the arrangement includes at least a tree with a plurality of subtrees, each rotation gate corresponding to a subtree. The technique includes iteratively generating a directed acyclic graph (DAG) of the quantum circuit, where a front layer of the DAG is a set of rotations that can be effectively implemented at each iteration. The technique includes selecting a subset of the rotations (a 'selected subset') in the front layer in which the subtrees are arranged not to intersect (“non intersecting subsets”).

Compilation technique for surface code architecture

The disclosure refers to method for converting an input quantum circuit comprising gates into an output quantum circuit compliant with execution constraints, comprising: determining if a front layer comprises single-qubit gates, and updating the front layer; reiterating the determining step as long as the front layer comprises single-qubit gates; identifying in the front layer a quantum gate that does not satisfy execution constraints; determining a pattern such that the gate satisfies the execution constraints when applying the adjoint pattern to the gate; adding the pattern to the output quantum circuit, and applying the a joint pattern to the gate; and reiterating these steps until each quantum gate in the input quantum circuit satisfies the execution constraints; wherein each pattern is determined in such a way that a number of CNOT-gates comprised by at least one pattern is minimized.

Method for transforming a quantum circuit while minimizing the CNOT-cost

A method for generalizing an algorithm configured to synthesize a diagonal product of Pauli rotations to synthesize a product of Pauli rotations comprising X, Y and Z rotations, the method comprising:

Method for synthesizing product of Pauli rotations in a quantum circuit and process for synthesizing quantum circuits for Trotter-Suzuki n-order expansion

This invention relates to a method of building a hybrid quantum-classical computing network, comprising: a first step of transformation of an application composed of services into a Petri net including both Petri places () and Petri transitions (-) between said Petri places (), any said Petri place () corresponding to: either a first type building block corresponding to any quantum processing unit () which processes a job into a result, or a second type building block corresponding to any plugin unit (), which converts a job into another job and/or a result into another result, any Petri transition (-) corresponding to any link between two building blocks (), all said links (-) being formatted so as to make any building block () interchangeable, a second step of transformation of said Petri net into a hybrid quantum-classical computing network, replacing any building block by its corresponding unit (), interconnecting all said corresponding units () together by replacing any Petri transition (-) by a connection simply transmitting without processing nor converting.

Method of building a hybrid quantum-classical computing network

A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a separation of the quantum circuit into local layers, and entangling layers; compiling the local layers; compiling the entangling layers, separate from the step of compiling the local layers, transforming the quantum gates of those entangling layers so that they contain only collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category; and a step of grouping together the compiled local layers and the compiled entangling layers into a compiled quantum circuit.

Method for compiling a quantum circuit on a trapped-ion quantum processor

A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.

Method for development of a compiling process for a quantum circuit on a quantum processor and said method

The present disclosure relates to a compiling method () for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S) append the partial quantum sub-circuit to the output quantum circuit.

Compiling method and system with partial synthetization of quantum computer compliant quantum circuits

Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.

Compiling on interconnected qubit subsystems

Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.

Quantum computing compiling

A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing only a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a step of compiling the quantum gates so that they only contain collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category, and so that all or at least some of those collective or entangling quantum gates simultaneously apply to at least three qubits, advantageously simultaneously apply to the majority of qubits, and even more advantageously simultaneously apply to all the qubits; and a step of grouping together the compiled quantum gates in a compiled quantum circuit.

Method for compiling a quantum circuit on a quantum processor with trapped ions

A method for developing a method for compiling a quantum circuit on a quantum processor, comprising:

Method for developing a process for compiling a quantum circuit on a quantum processor and such process

Disclosed is a method for optimizing a quantum circuit of an ordered series of quantum gates, applied to an initial layout of qubit values, consisting in inserting a set of local SWAP gates so that all gates of the circuit are local, the method including: for each gate, if it is not local, inserting a set of local SWAP gates; determining the set of permutations, each consisting of a succession of swaps of qubit values along shortest paths between positions of qubits associated with the gate; and choosing, from the permutations, a permutation that minimizes a cost representing the number of swaps necessary to make the gates of a sequence within the series, of substantially smaller size, local; re-establishing the initial layout by establishing a tree covering a graph representative of the layout of the qubits of the circuit, and by swapping qubit values along paths of the tree.

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Versailles, France

Simon Martiel