Intel Corporation

Simon M Tam

Mark A Holler

Stefan Rusu

Hernan Adolfo Castro

Valluri Ramana Rao

Richard H Livengood

Rahul D Limaye

Steve Seidel

Utpal Desai

Ian A Young

Alan H Kramer

Alper Ilkbahar

Daniel N Tang

Stefan K Lai

George R Canepa

John Wai Fu

Ronald G Benson

Simon Y Wang

Himanshu Choksi

Duane H Oto

Winston K Lee

A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Power supply voltage droop compensated clock modulation for microprocessors

An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

Apparatus for thermal management of multiple core microprocessors

In one embodiment, the present invention includes a method. In the method, a fiducial transistor is provided in an integrated circuit. Also in the method, a power conductor is coupled to a first terminal of the transistor. Also in the method, a ground conductor is coupled to a second terminal of the transistor. Also in the method, a control conductor is coupled to a third terminal of the transistor. Also in the method, other circuitry is provided, the other circuitry is operatively decoupled from the fiducial transistor and the other circuitry is operable without the fiducial transistor.

Fiducial transistor in an integrated circuit

A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Adaptive variable frequency clock system for high performance low power microprocessors

A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.

VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors

Method and apparatus for making and using a beacon fiducial for an integrated circuit

An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.

Method and apparatus to reduce clock jitter of an on-chip clock signal

A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.

Multiple synthesizer based timing signal generation scheme

The invention comprises, in one aspect, a content addressable memory array having a plurality of memory locations to store tag words. The content addressable memory array includes a parity encoder and a parity comparator. The parity encoder has a first input terminal to receive an input data signal and a first output terminal to deliver a signal representative of the parity of the input data signal. The parity comparator has a second input terminal, a third input terminal connected to the first output terminal, and a plurality of memory cells to store original parities of the tag words. The parity comparator compares the original parity of a first tag word to the parity of the input data signal in response to a receiving a match signal. The content addressable memory array includes a fourth input terminal to receive the input data signal, and a second output terminal to send the match signal in response to one of the tag words matching the input data signal. The second output terminal connects to the second input terminal.

Method and apparatus for detecting soft errors in content addressable

A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed. Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.

Method of increasing the accuracy of an analog circuit employing

A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one of a pair of complementary input voltages. The floating gate devices also have complementary threshold voltages such that packets of charge are produced from the synapse cells that are proportional to the difference between the input and voltage threshold. The charge packets are accumulated by the pairs of column lines in the array.

Difference calculating neural network utilizing switched capacitors

In an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values in pairs of floating gate transistors. A long-tail pair differential transconductance multiplier is synthesized by selectively using the floating gate transistor pairs as the current source. Appropriate transistor pairs are multiplexed into the network for forming a differential output current representative of the product of the input vector component applied to the differential input and the stored reference vector component stored in the multiplexed transistor pair that is switched into the multiplier network to function as the differential current source. Pipelining and output multiplexing is also described in other preferred embodiments for increasing the effective output bandwidth of the network.

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Redwood City, CA, United States of America

Simon M Tam