Xerox Corporation

Simon M Law

Li-Fung Cheung

Daniel H Greene

Mehrdad Zomorrodi

Jean-Swey Kao

Dung N Tran

Bruce Long

Thien M Ngo

Thierry L Watteyne

Many compression algorithms require the compressor to generate trees (tables) for encoding purposes. To generate the optimum tree for a set of Huffman symbols either takes too much time or requires too much hardware. This invention proposes to separate the symbols into groups according to the symbol's occurring frequency. With these groups of symbols available, subsequent code length assignment of these groups can be done without a complete sorting of all the symbols and their parents. During code length assignment, some relocation of individual symbols from one group to another can also be performed to optimize the Huffman table. In most of the cases this technique can achieve a compression ratio within 5% of the optimum Huffman table, while requiring less hardware or software overhead.

Method of building an adaptive huffman codeword tree

A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the 'history', stored in a series of shift registers. Each register and associated comparator constitutes a cell. If one or more matches are found the history data is shifted one pixel, the non-matching cells are disabled, and the next input pixel is compared against the contents of the same cells that had the previous matches. The matching is terminated when the longest series of matching pixels is found. The output code is then the length of the matching series of pixels, and the displacement of the first input pixel from the first matching pixel. An encoder generates an initialize signal that resets all of the disabled cells on the same clock cycle on which the output code word is generated. To make the circuit more compact, the cells can be arranged into a square format with one output line for each row and column from the cells to the encoder.

String-match array for substitutional compression

A new and improved decoder for decoding CCITT compressed image data. This decoder separates all the incoming codes into short codes and long codes. The short codes are sent to the short channel decoder and the long codes are sent to the long channel decoder. At each decoding cycle either the long channel decoder or the short channel decoder is active. The short channel decoder has a twin set decoder which decodes two short codes in parallel and guarantees two bits of decompressed data per decoding cycle. If the decoding of a first code generates a decompressed data of only one bit, then the decompressed data of a second code will be combined with the first decompressed data and the combination will be sent out. This process guarantees at least two bits of decompressed data per decoding cycle. The long channel decoder decodes the long intermediate codes which always generate at least four bits of decompressed data.

High speed CCITT decompressor

A minimum delay, high speed, tri-state bus driver is utilized to couple data and control signals to a memory bus with a minimum amount of buffering. Two transistors 24, 26, utilized in a bootstrap configuration, deliver a system clock to the gate terminals of output transistors 28, 30 which are coupled to the memory bus 40. The input data signals and accompanying control signals are applied to these bootstrap transistors 24, 26 via push/pull amplifiers 20, 22 and, depending on the data level of the input data signal, either a logic 1, a logic 0, or a high impedance open circuit is applied to the bus.

Minimum delay high speed bus driver

A weighted capacitor digital to analog converter is disclosed which requires only one stage and one conversion step. By the use of two reference voltages and two groups of capacitors in parallel, various capacitors in these groups can be selectively switched from the reference voltages to ground potential in response to input binary digit signals thereby presenting a predetermined amount of voltage to the output amplifier depending upon the number and particular combination of capacitors switched or non-switched to ground.

Two reference voltage weighted capacitor digital to analog converter

A weighted capacitor digital to analog converter is disclosed which requires two stages but only one conversion step. By the use of an applied reference voltage and two groups of capacitors, the outputs of each group being coupled to an amplifier and feedback capacitor circuit, various capacitors in these groups can be selectively switched from the reference voltage to ground potential in response to input binary digit signals thereby presenting a predetermined amount of voltage to the output amplifiers depending upon the number and particular combination of capacitors switched or non-switched to ground.

Two stage weighted capacitor digital to analog converter

An integrated circuit chip with digital and analog circuits thereon for providing a low cost infrared reflectance densitometer for detecting relative toner density on a photoreceptive surface including several stages of calibration including photodiode detection means 208 for monitoring and controlling the light output from a light emitting diode 206, photodiode means 302 for detecting undesired scattered and reflected background light signals, further photodiode means 304 for detecting the light reflected from said photoreceptive surface as may be affected by toner deposited thereon, an automatic gain control circuit 400 for automatically adjusting the output gain of the reflectance densitometer, and sample and hold circuit means 600 for adjusting the circuit for different effects of the aging, leakage current effects, or other undesired performance characteristics of the circuit components.

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Torrance, CA, United States of America

Simon M Law