Other

Sony Corporation

Sony Electronics Inc

Simon Kim

Sheng Hung Wang

Hidekazu Watanabe

Handiono Santosa

Wang Sheng Hang

In one embodiment of the present invention, a bus controller is used in a multi-master system having first and second processors. The bus controller includes a bus arbiter and a first multiplexer. The bus arbiter is coupled to the first and second processors via first and second master buses, respectively, to generate an arbitration select signal based on result of arbitrating bus access information from the first and second processors. The first multiplexer is coupled to the first and second master buses and a first slave bus in a plurality of slave buses to provide device access information selected from the bus access information using the arbitration select signal. The device access information is transferred to a first slave device connected to the first slave bus.

Effective bus utilization using multiple buses and multiple bus controllers

In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals. The mapping circuit stores mapping information to dynamically map an address space of K slave devices coupled to K slave buses based on the arbitration signals. The switching circuit connects the N master buses to K slave buses based on the arbitration signals and the mapping information.

Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses

A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.

Method and apparatus for quick clock swapping using much slower asynchronous clock for power savings

In one embodiment of the present invention, an oscillator activator includes a trigger circuit, a controller, and a stability generator. The trigger circuit generates a trigger signal based on a reset signal. The controller controls generation of an oscillator signal from a main oscillator based on the reset signal. The stability generator generates a stability indicator signal in response to the trigger signal. The stability indicator signal indicates a stable condition of the main oscillator corresponding to a start-up time of the main oscillator.

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Vista, CA, United States of America

Simon Kim