Maxim Integrated Products, Inc.

Wolfson Microelectronics Limited

Simon Kenneth Quinn

Rajdeep Mukhopadhyay

Andrew James Howlett

Matt Felder

Ross Ballany

Euan Patrick Murphy

Sergei Slavnov

An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals.

Audio amplifier having idle mode

A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.

Digital pulse width modulation driver system

A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout&#x2212;). An array of further capacitors (C-CN) correspond in number at least to the number of data bits (D-DN) to be converted. The capacitors (Cf, C-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P) in which the further capacitors are connected (S, S) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P) in which the further capacitors are connected (S) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P) in which the parallel connected further capacitors are connected (S, S) in parallel with the first capacitor. The equalization phase masks nonlinearities arising in switches (S) and thereby improves harmonic distortion.

Digital to analog converter circuits and methods of operation thereof

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Edinburgh, United Kingdom

Simon Kenneth Quinn