Graphcore Limited

Simon Jonathan Stacey

Stephen Felix

Phillip Horsfield

Yang Chih Wang

A substrate and a method for manufacturing the substrate. The substrate is suitable for mounting at least one semiconductor die onto a printed circuit board. The substrate comprises two opposing stacks, with each stack comprising alternating layers of copper and electrically insulating film. The film and the copper have different co-efficients of thermal expansion, allowing the warpage behaviour of the substrate to be controlled by providing the substrate with different film thicknesses between the opposing stacks.

Controlling warpage of a substrate for mounting a semiconductor die

A memory and routing module includes a substrate and a connection component. The connection component is attached to the substrate and includes multiple pins that connect the module to a corresponding connection component on a motherboard. The substrate is connected to a dynamic random-access memory, DRAM, chip, and a routing chip. The routing chip includes a memory controller, multiple connections, and routing logic. The multiple connections include a first group between the memory controller and the DRAM chip and a second group of connections with the pins of the connection component. The routing logic routes data between the second group of connections and the first group of connections.

Memory and routing module for use in a computer system

The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.

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Bristol, United Kingdom

Simon Jonathan Stacey