Cambridge Silicon Radio Limited

Qualcomm Technologies International, Ltd.

Ams Sensors UK Limited

Sciosense B.v.

Avago Technologies Fiber IP (singapore) Pte. Ltd

Simon Jonathan Stacey

Vlad Lenive

Syed Zeeshan Ali

Matthew Govett

Florin Udrea

Kaspars Ledins

Clinton Sean Dixon

Douglas James McMillan

A gas sensor with a gas permeable region is disclosed. In an embodiment a gas sensor includes a dielectric membrane formed on a semiconductor substrate having a cavity portion, a heater located within or over the dielectric membrane, a material for sensing a gas, wherein the material is located on one side of the dielectric membrane, a support structure located near the material, a gas permeable membrane coupled to the support structure so as to protect the material, wherein the semiconductor substrate forms the support structure.

Gas sensor with a gas permeable region

We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.

Electronic device

We disclose herein a method for heating a gas sensing material formulation on a microhotplate which comprises: a dielectric membrane formed on a semiconductor substrate comprising an etched portion; and the gas sensing material formulation being located on one side of the dielectric membrane. The method comprising: selectively heating the gas sensing material formulation using an infra-red (IR) heater located over the substrate, and controllably cooling the semiconductor substrate using a cooling baseplate provided under the substrate and using an insulating medium located between the substrate and the cooling base plate so that a gas sensing structure is formed on said one side of the dielectric membrane from the gas sensing material formulation.

Sensing layer formation

We disclose herein a method for testing a batch of environmental sensors to determine the fitness for purpose of the batch of environmental sensors, the method comprising: performing a plurality of electrical test sequences to the sensor inputs of the batch of environmental sensors to measure electrical responses of the sensor outputs of the batch of environmental sensors; correlating the measured electrical responses from the batch of environmental sensors to predetermined environmental parametric ranges of at least one environmental sensor so as to define correlated electrical test limits; and determining the fitness for purpose of the batch of environmental sensors if the measured electrical responses are within the correlated electrical test limits.

Environmental sensor test methodology

We disclose herein an environmental sensor system comprising an environmental sensor comprising a first heater and a second heater in which the first heater is configured to consume a lower power compared to the second heater. The system also comprises a controller coupled with the environmental sensor. The controller is configured to detect if a measured value of a targeted environmental parameter is present. The controller is configured to switch on at least one of the first and second heaters based on the presence and/or result of the measured value of the targeted environmental parameter.

Environment sensor system

A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.

Chip mounting

A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Composite reconstituted wafer structures

A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.

An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.

Interconnection structure

A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.

Multi-chip package

A method of providing connections to a chip having contact pads on the surface thereof, comprising: locating a discrete solder element on each pad; and melting the discrete solder elements so as to cause each of them to adhere to the respective pad, thereby forming a solder bump extending from the surface of the chip; wherein the size of each discrete solder element relative to the area of the pad on which it is located is such that the height of each bump is less than 70% of the diameter of the solder element that formed it.

Formation of solder bumps

An optoelectronic device having a semiconductor laser diode and a grating structure for stabilizing the optical wavelength of optical radiation generated by the laser diode.

Growing community of inventors

Ely, United Kingdom

Simon Jonathan Stacey