Zarlink Semiconductor Limited

Mitel Corporation

Zarliak Semiconductor Inc.

Simon John Skierszkan

Hazem Abdel-Maguid

Youcef Fouzar

Wenbao Wang

Ranjit Singh

Robert Van Der Valk

Jim Lehmann

A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Frame boundary discriminator

A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.

Timing circuit with dual phase locked loops

A voltage controlled oscillator generates an output signal whose frequency varies as a first function of a control voltage applied to a control terminal. The voltage controlled oscillator has a wide range of frequency of operation. A gain adjust circuit adjusts the gain of the voltage controlled oscillator such that the first function varies as a second function of the gain. In a preferred embodiment the gain adjust circuit includes a variable impedance that may be external or integrated onto a common chip with the oscillator core.

Capture range control mechanism for voltage controlled oscillators

A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL. The second DCO of the output PLL has a control input to introduce a phase offset therein relative to the first DCO of the output PLL. A control unit for sets the phase of the second DCO of the acquisition circuit and the second DCO of the output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.

Multiple input phase lock loop with hitless reference switching

A digital phase locked loop (PLL) for recovering a stable clock signal from at least one input signal subject to jitter. The PLL has a digital controlled oscillator for generating a desired output and a stable local oscillator or providing clock signals. A plurality of hierarchical, multi-stage delay lines are provided to generate the required output frequencies for stable T1, E1 and ST3/OC3 timing references.

Reduced jitter phase lock loop using a technique multi-stage digital delay line

Serial bit rate converter embedded in a switching matrix

A frequency doubler for receiving an input clock signal and generating an output signal at twice the input signal frequency and having fifty percent duty cycle. The input signal is received by a tapped delay line and transmitted from a predetermined tap thereof to a first input of an EXCLUSIVE OR gate. The second input of the EXCLUSIVE OR gate receives the undelayed input clock signal and generates the output clock signal in response to performing an EXCLUSIVE OR operation on the delayed and undelayed signals. The duty cycle of the output signal is monitored via a comparator in combination with logic circuitry. The output of the comparator is connected to the up/down input of a digital counter which is clocked once for each cycle of the input signal, and generates a digital count value in response thereto. In the event that the monitored duty cycle is less than fifty percent, the comparator generates an up count signal for incrementing the digital counter. In the event that the duty cycle is greater than fifty percent, the comparator generates a down count signal for decrementing the counter. The counter output is connected to a decoder circuit for decoding the digital count valve and generating a signal to enable one of the taps of the delay line, thereby compensating for drift in the components comprising the delay line, and maintaining the output signal at fifty percent duty cycle.

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Stittsville, Canada

Simon John Skierszkan