Texas Instruments Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Simon John Molloy

Christopher Boguslaw Kocon

Hideaki Kawahara

John Manning Savidge Neilson

Osvaldo Jorge Lopez

Jonathan Almeria Noquil

Nace Layadi

Seetharaman Sridhar

Thomas Eugene Grebs

Satoshi Suzuki

Hong Yang

Walter Hans Paul Schroen

Sailesh Mansinh Merchant

Daniel Joseph Vitkavage

Bailey R Jones

Sean Lian

Tom Grebs

Edward Belden Harris

Charles Walter Pearce

Brittin C Kane

John Martin McIntosh

Haian Lin

Sidhartha Sen

Thomas Craig Esry

Mario V Pita

Sylvia Marci Luque

Gary Eugene Daum

Jayhoon Chung

Pradip Kumar Roy

David John Baldwin

Isik C Kizilyalli

Kuo-Hua Lee

Kurt George Steiner

Vivian Wanda Ryan

Erik Cho Houge

Abidur Rahman

Hao Wu

Catherine B Vartuli

Sylvia Thomas

Allen Yen

Steven Alan Lytle

Scott Jessen

James W Blatchford, Jr

Donald C Dennis

Brian David Crevasse

Boling Wen

John C Desko, Jr

Tatsuya Tominari

A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

Integrated channel diode

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Photo-sensitive silicon package embedding self-powered electronic system

A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Medium high voltage MOSFET device

A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

Power transistor with terminal trenches in terminal resurf regions

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Vertical high-voltage MOS transistor

Medium voltage MOSFET device

A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Multiple shielding trench gate FET

A self-powered electronic system comprises a first chip () of single-crystalline semiconductor embedded in a second chip () of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container () bordered by ridges (). The flat side () of the slab includes a heavily n-doped region () forming a pn-junction () with the p-type bulk. A metal-filled deep silicon via () through the p-type ridge () connects the n-region with the terminal () on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

A packaged electronic system comprises a slab () of low-grade silicon (l-g-Si) configured as ridges () framing a depression of depth () including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals () connected to attachment pads in the central area; and semiconductor chips () having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Silicon package having electrical functionality by embedded passive components

A packaged transistor device () comprises a semiconductor chip () including a transistor with terminals distributed on the first and the opposite second chip side; and a slab () of low-grade silicon (l-g-Si) configured as a ridge () framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth () at least equal to the chip thickness, the ridge covered by device terminals () connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals () of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Silicon package for embedded semiconductor chip and power converter

An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.

Silicon package for embedded electronic system having stacked semiconductor chips

A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.

Silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench

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Allentown, PA, United States of America

Simon John Molloy