Arm Limited

Apical Limited

Simon John Craske

Antony John Penton

Richard Roy Grisenthwaite

Michael John Williams

Thomas Christopher Grocutt

Peter Richard Greenhalgh

Ian Michael Caulfield

Max John Batley

John Michael Horley

Allan John Skillman

Andrew Christopher Rose

Paul Kimelman

Eric Jason Furbish

Peter Logan Harrod

Simon Axford

Jonathan William Brawn

Stuart David Biles

Nigel John Stephens

Edmond John Simon Ashfield

Andrew John Turner

Thomas Sean Houlihane

Paul Anthony Gilkerson

Michael Alexander Kennedy

Chiloda Ashan Senerath Pathirane

Michael John Gibbs

David Michael Gilday

Richard Anthony Lane

Loïc Pierron

Mittu Xavier Kocherry

Daren Croxford

David James Seal

Jason Parker

Paul Gilbert Meyer

Frederic Claude Marie Piry

Alex James Waugh

Simon Andrew Ford

Vladimir Vasekin

David James Williamson

Alasdair Grant

François Christopher Jacques Botman

Paul Stanley Hughes

Gilles Eric Grandou

Kauser Yakub Johar

Alexander Alfred Hornung

Jacob Eapen

Yuval Elad

Carlo Dario Fanara

Mark Gerald LaVine

Melanie Emanuelle Lucie Teyssier

Bradley John Smith

Alexander Donald Charles Chadwick

Anthony John Goodacre

Nicolas Jean Phillippe Huot

Richard York

Jean Sébastien Leroy

Max Zardini

Uma Maheswari Ramalingam

Paul Gilkerson

There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

Lookup circuitry for secure and non-secure storage

An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

Apparatus and method

An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.

Apparatus and method for triggering action

A multiplier array for implementing a multiply-accumulate operation has a plurality of rows, where each row comprises multiplexer circuitry and adder circuitry, the multiplexer circuitry selecting, in dependence on a control input, one of a first multiplexer input value and a second multiplexer input value to provide as a first adder input value to the adder circuitry. In each row other than an initial row, the adder circuitry also receives as a second adder input value at least a portion of a result value produced in a preceding row. In a multiplication mode, the multiplier array implements the multiply-accumulate operation, and in a linear interpolation mode, the multiplier array implements a linear interpolation operation between a lower limit value and an upper limit value based on a weighting value.

Apparatus and method for performing linear interpolation

An apparatushas a processing pipelinesupporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structureis accessible in both the first and second processing modes. When the second processing mode is selected, control circuitrytriggers a subsetof the entries of the storage structure to be placed in a power saving state.

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

Deferred system error exception handling in a data processing apparatus

A data processing apparatus () operates in a first mode of operation having a first set of processing circuitry () ready to perform processing operations and in a second mode of operation having a second set of processing circuitry () ready to perform processing operations. A first proper subset () of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. A second proper subset () of program instructions within the instruction set are required to be processed by the processor operating in the second mode. Processing circuitry () which is inactive in a mode of operation may be placed into a low power state.

Variable-length-instruction processing modes

An apparatus () comprises one or more bounded pointer storage element () each to store a pointer () having associated range information () indicating an allowable range of addresses for the pointer (). Processing circuitry () performs, in response to a first type of instruction () identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information () associated with the pointer stored in the given bounded pointer storage element ().

Apparatus and method for executing instruction using range information associated with a pointer

Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

Register-provided-opcode instruction

Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided. Decoding circuitry generates control signals in dependence on the instructions of the sequence of instructions, wherein the decoding circuitry is responsive to instructions in a first subset of an instruction encoding space to generate the control signals to control the execution circuitry to perform the first data processing operations, and the decoding circuitry is responsive to instructions in a second subset of the instruction encoding space to generate the control signals in dependence on a configuration condition: to generate the control signals for the auxiliary execution circuitry interface when the configuration condition has a first state; and to generate the control signals for the coprocessor interface when the configuration condition has a second state.

Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry

A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

Error correcting bits

Exception control circuitry controls exception handling for processing circuitry. In response to an initial exception occurring when the processing circuitry is in a given exception level, the initial exception to be handled in a target exception level, the exception control circuitry stores exception control information to at least one exception control register associated with the target exception level, indicating at least one property of the initial exception or of processor state at a time the initial exception occurred. When at least one exception intercept configuration parameter stored in a configuration register indicates that exception interception is enabled, after storing the exception control information, and before the processing circuitry starts processing an exception handler for handling the initial exception in the target exception level, the exception control circuitry triggers a further exception to be handled in a predetermined exception level.

Exception interception

Apparatus for processing data () includes issue circuitry () for issuing program instructions (processing operations) to execute either within real time execution circuitry () or non real time execution circuitry (). Registers within a register file () are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry () responds to a trigger event to enter a real time issue policy mode to control the issue circuitry () to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.

Instruction issue according to in-order or out-of-order execution modes

An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction. This provides a mechanism for allowing an apparatus to perform operations required by debug instructions in situations where the processing circuitry hardware is not able to natively perform those operations in response to the specified debug instruction.

Apparatus and method for executing debug instructions

An apparatus and method are provided for performing data processing operations. The apparatus has processing circuitry for performing data processing operations configured to operate in a normal mode and a memory region management mode. A memory is used to store data accessed by the processing circuitry when performing the data processing operations. A memory region table is provided to define accessibility control information for each of a number of memory regions within the memory. An access control mechanism controls access to the memory in response to an access request issued by the processing circuitry, and a memory protection unit providing a bypass indication for one or more memory regions is referenced by the access control mechanism when the processing circuitry is in the memory region management mode. The access control mechanism is arranged to constrain access to the memory location identified by the access request based on the accessibility control information defined in the memory region management mode when the processing circuitry is operating in the normal mode. When the processing circuitry is operating in the memory region management mode, the access control mechanism is arranged to reference the memory protection unit and when the bypass indication is set for the memory region, to process the access to the memory location unconstrained by the memory region table.

Apparatus and method for handling memory access requests

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Cambridge, United Kingdom

Simon John Craske