Micron Technology Incorporated

Round Rock Research, LLC

Other

Simon J Lovett

Dean D Gans

Brian P Higgins

Richard Edward Fackenthal

Thomas J Pawlowski

John Frederic Schreck

Brian M Shirley

Cliff Zitlaw

Hiroshi Akamatsu

Roger D Norwood

Daniele Vimercati

Jeffrey P Wright

Donald M Morgan

J Thomas Pawlowski

Sujeet V Ayyapureddi

Jongtae Kwak

Larren Gene Weber

Victor Wong

William F Jones

Mark K Hadrick

Methods, systems, and devices for memory operations are described. First scrambling sequences may be generated for first addresses of a memory device after an occurrence of a first event, where the first addresses may be associated with commands received at the memory device. Portions of the memory array corresponding to the first address may be accessed based on the first scrambling sequences. After an occurrence of a subsequent event, second scrambling sequences may be generated for the first addresses, where the second scrambling sequences may be different than the first set of scrambling sequences. After the occurrence of the subsequent event, the portions of the memory array may be accessed based on the second scrambling sequences.

Data invalidation for memory

Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

Apparatuses and methods for countering memory attacks

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

Systems, methods, and apparatuses for temperature and process corner sensitive control of power gated domains

Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.

Power-efficient generation of voltage

Memory devices including word lines coupled to pull-down transistors are disclosed. A memory device may include a number of memory cells, a first word line, and a second word line. The first word line may be configured to apply a voltage to a number of transistors to access at least one of the number of memory cells. The first word line may include a first portion electrically coupled to a first driver and a second portion electrically coupled to a gate of a pull-down transistor. The second word line may be positioned adjacent to the first word line. The second word line may include a third portion electrically coupled to a second driver and a fourth portion electrically coupled to a terminal of the pull-down transistor. Associated systems are also disclosed.

Word lines coupled to pull-down transistors, and related devices, systems, and methods

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.

Plate defect mitigation techniques

Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.

Memory device latch circuitry

A semiconductor device may include a local power domain configured to selectively provide or prevent power to a logic block of the memory device and a temperature sensor located on the semiconductor device. The semiconductor device may also include timeout circuitry to delay a power down of the local power domain by a timeout time based at least in part on temperature information from the temperature sensor.

Setting local power domain timeout via temperature sensor systems and methods

Array plate short repair

Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.

Repair fuse latches using static random access memory array

A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

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Boise, ID, United States of America

Simon J Lovett