Intel Corporation

Simon Hughes

Andreas Langer

Daniel B Schwartz

Gregory W Chance

Nebil Tanzi

Niranjan Karandikar

Wayne Ballantyne

Peter Pawliuk

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Techniques for addressing phase noise and phase lock loop performance

Sequence trigger circuitry may be configured to repeat command sequences to switch between communication modes of a RFFE. The circuitry may include a first logic circuitry to, in response to a trigger signal, generate a first output signal or a second output signal to activate a first command sequence or a second command sequence, respectively. The circuitry may also include a second logic circuitry to activate a third command sequence based on a comparison of a clock output signal with a first timer value and upon generating the first output signal. The first command sequence and the third command sequence may switch the RFFE into a receive mode of the plurality of modes. The circuitry may include a third logic circuitry to activate a fourth command sequence based on a comparison of the clock output signal with a second timer value and upon generating the second output signal.

Sequence triggering in RF front-ends

A tunable matching network is configured to couple at least one filter with a power amplifier that is configured to operate in an envelope tracking (ET) mode of operation over a transmit band. A control component is configured to detect a present set of operating conditions of the power amplifier when the power amplifier operates in the ET mode of operation. The present set of operating conditions comprises a present frequency of operation, and the control component is further configured to transmit a control signal to the tunable matching network in response to the detected present set of operating conditions. The tunable matching network is further configured to adjust an impedance of the tunable matching network in response to the transmitted control signal such that one or more ET characteristics are optimized based at least in part on the present set of operating conditions.

Method and apparatus for correcting inconvenient power amplifier load characteristics in an envelope tracking based system

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Chandler, AZ, United States of America

Simon Hughes