Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Simon Gallimore

Dale John McQuirk

Miten H Nagda

Nidhi Chaudhry

Stefano Pietri

Mohit Arora

James Robert Feddeler

Lawrence Loren Case

Charles Eric Seaberg

Garima Sharda

Colin MacDonald

Prashant Bhargava

James H Carlquist

Charles E Cannon

Edevaldo Pereira Da Silva, Jr

Akshat Gupta

Glen G Wienecke

Bradley G Hoskins

Deepak Negi

Vimal Rajput

A method and system are provided for supplying power to a backup power domain by connecting a battery voltage to a supply terminal for a backup power domain in a low power microcontroller during a startup mode when a main supply voltage, by detecting application of the main supply voltage to the low power microcontroller at a predetermined safe voltage level, and by activating a selection control circuit to power the backup power domain in the low power microcontroller from the main power supply voltage or the backup power supply voltage based on a software-controlled configuration bit, where the selection control circuit is configured to connect, in response to the software-controlled configuration bit having a first user-selected value, the main power supply voltage to the supply terminal for the backup power domain when the main power supply voltage is smaller than the battery power supply voltage.

Robust fail-safe system for prolonging the backup battery life in real-time low power MCU systems

A first voltage scaling power switch is coupled to a first power supply terminal for providing power to a first circuit portion, and a second voltage scaling power switch is coupled between the first power supply terminal providing power to a second circuit portion. A common power rail is coupled the first and second power input nodes during respective voltage scaling modes of the first and second circuit portions. A feedback circuit coupled to the common power rail provides a feedback signal to a control input of the first voltage scaling power switch to regulate a voltage provided by the first power switch, and to a control input of the second voltage scaling power switch to regulate a voltage provided by the second voltage scaling power switch.

Circuit with multiple voltage scaling power switches

An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Multiprocessing system with peripheral power consumption control

A resource domain controller in a data processing system stores information that is used to group various resources, such as bus masters and peripherals, into common domains. Each group can be referred to as a resource domain and can include one or more data processor and peripheral devices. The resource domain information is then used to determine whether a particular access request from a data processor is authorized to access its intended target, e.g., one of the peripheral devices, by determining whether the access request and the intended target each belong to a common resource domain. If so, the access request is allowed, otherwise the access request is prevented from being successfully completed.

Resource domain partioning in a data processing system

A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

Data processing system with temperature monitoring for security

A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.

Programmable buffer system

A fractional frequency divider counts pulses of a digital input clock signal and enables a clock gating module when a preset count is reached. The clock gating module combines the outputs of two clock gating cells that receive, respectively, the input clock signal and an inverted version of the input clock signal. Output pulses are produced on both positive and negative edges of the input clock signal. This permits generation of output clock pulses that can be set to have a spacing and width granularity of half an input clock period, giving the advantages of low jitter and fine duty cycle control.

Fractional frequency divider

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Austin, TX, United States of America

Simon Gallimore