Commissariat a L'energie Atomique

Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Simon Deleonibus

Maud Vinet

Jean-Marie Basset

Gilles Marchand

Paul-Henri Haumesser

Catherine Santini

Thibaut Gutel

Paul Campbell

Laurent Clavelier

Thomas Ernst

Bernard Previtali

François Andrieu

Bernard Guillaumot

Fran&ccedil;ois Martin

David Fraboulet

Georges Guegan

Gilles Fanget

Christian Caillat

Fabien Coudert

A method for making electrical interconnections of carbon nanotubes, including a) depositing an ionic liquid including nanoparticles of at least one suspended electrically conducting material, covering at least one surface of an element configured to be used as a support for carbon nanotubes, b) forming a deposit of the nanoparticles at least against the surface of the element, c) removing the remaining ionic liquid, d) growing carbon nanotubes from the deposited nanoparticles, and further including between the c) removing the remaining ionic liquid and the d) growing carbon nanotubes, passivating the deposited nanoparticles not found against the surface of the element.

Method for making electrical interconnections with carbon nanotubes

A method for producing a memory device with nanoparticles, including steps of: a) forming, in a substrate based on at least one semi-conductor, source and drain regions, and at least one first dielectric on at least one zone of the substrate arranged between the source and drain regions and intended to form a channel of the memory device, b) depositing of at least one ionic liquid that is an organic salt or mixture of organic salts in a liquid state, wherein nanoparticles of at least one electrically conductive material are suspended in the ionic liquid, said ionic liquid covering at least said first dielectric, c) forming a deposition of said nanoparticles at least on said first dielectric, d) removing the ionic liquid remaining on the first dielectric, and e) forming at least one second dielectric and at least one control gate on at least one part of the nanoparticles deposited on the first dielectric.

Method for producing a conductive nanoparticle memory device

The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.

Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor

Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.

Method of producing a transistor

According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly () formed above the drain () comprises insulating zones () either side of the drain; cavities extend under the insulating assembly, either side of the channel (); the gate (a,b) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.

Method for making a vertical MOS transistor with embedded gate

The normally on transistor comprises a source, a drain and a channel. The source, drain and channel materials are chosen such that, for a NMOS type transistor, the electronic affinity of the drain material is lower than the electronic affinity of the channel material and the electronic affinity of the source material is higher than the electronic affinity of the channel material. Moreover, the materials are selected such that, for a PMOS type transistor, the upper level of the valence band of the drain material is higher than the upper level of the valence band of the channel material and the upper level of the valence band of the source material is lower than the upper level of the valence band of the channel material.

Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same

The field effect transistor comprises a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator. The channel is formed by a diamond-like carbon layer. The method for making the transistor successively comprises deposition of a diamond-like carbon layer on a substrate, deposition of a gate insulating layer and deposition of at least one conducting layer. The conducting layer is etched to form the gate electrode. Then an insulating material is deposited on the flanks of the gate electrode to form a lateral insulator. Then the gate insulating layer is etched and the diamond-like carbon layer is etched so as to delineate the channel. Then a semi-conducting material designed to form the source and a semi-conducting material designed to form the drain are deposited on each side of the channel.

Method for making a field effect transistor with diamond-like carbon channel and resulting transistor

The semi-conducting support comprises a graphite substrate having a front surface and a rear surface and at least a first stack arranged on the front surface of the substrate. The first stack successively comprises a single-crystal diamond layer, an electrically insulating oxide layer and a semi-conducting layer. The support can comprise a second stack arranged on the rear surface of the substrate and comprising the same succession of layers as the first stack or comprising a polymer material layer. A thermal connection passing through the first and/or second stacks and connecting the graphite substrate to an external surface of the support enables heat to be removed. The method can comprise production of the semi-conducting layer by molecular bonding of rectangular silicon strips onto the oxide layer.

Rectangular semi-conducting support for microelectronics and method for making same

A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas of the conducting layer are rendered insulating by oxidation. Oxidation can comprise oxygen implantation and/or thermal oxidation. The material of the conducting layer and the oxygen can form a volatile oxide evaporating partly or totally. The conducting layer is preferably formed by first and second conducting layers. Thus, oxidation can be performed, after the mask has been removed, so that the surface of the second conducting layer is oxidized on the side walls and on the front face.

Method for delineating a conducting element disposed on an insulating layer, device and transistor thus obtained

A method for forming patterns which are aligned on either side of a thin film deposited on a substrate. The method includes depositing a first pattern layer on the thin film which may occur before or after the local etching of the thin film to form a first marking. The method includes etching the first pattern layer in order to form a first pattern and depositing a first bonding layer for covering the first marking and the first pattern. The method may include suppressing the substrate as well as etching the first bonding layer to form a second marking at the location of the first marking. The method includes depositing a second pattern layer, and etching the second pattern layer to form the second pattern.

Method for forming patterns aligned on either side of a thin film

A field-effect transistor including: a support substrate, an active area forming a channel; a first active gate which is associated with a first face of the active area; source and drain areas which are formed in the active area and which are self-aligned on the first gate; a second insulated gate which is associated with a second face of the active region opposite the first face of the active region. According to the invention, the second gate is self-aligned on the first gate and, together with the first gate, forms a mesa structure on a support substrate.

Field-effect transistor with horizontal self-aligned gates and the production method therefor

This invention relates to a process for a manufacturing a Coulomb blockade transistor. The process comprises the following steps in sequence: deposition on an insulating substrate of a source layer, a tunnel-insulating layer and an alternating stack of at least one conducting layer and at least one insulating layer, a first etching of the stack to form a filiform tab, coating of the filiform tab with an electrically insulating coating material, a second etching of the tab of the stack to form a pillar, the second etching preserving the coating material to define a groove on each side of the pillar, the formation of at least one isolated grid in the groove, and the formation of a drain in contact with one end of the pillar opposite the source layer, through at least one tunnel-insulating layer.

Processes for making a single election transistor with a vertical channel

An electronic memory having a source () and a drain () comprising on a substrate () a floating gate () and a control gate (). According to the invention, the floating gate () has a substantially U-shaped cross-section defining a space within which the control gate () is arranged.

Damascene architecture electronic storage and method for making same

A method for fabricating an electronic component with a self-aligned source, drain and gate. The method includes forming a dummy gate on a silicon substrate, in which the dummy gate defines a position for a channel of the component. The method also includes at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask, superficial, self-aligned siliciding of the source and drain, depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain. Further, depositing the at least one contact metal layer includes depositing a first metal layer and, above the first metal layer, a second metal layer having a greater mechanical resistance to polishing than the first metal layer. In addition, a thickness of the first metal layer is less than the height of the dummy gate, and a total thickness of the first and second layers is greater than the height of the dummy gate. Further, the first metal is chosen from among tungsten and titanium, and the second metal is chosen from among TaN, Ta and TiN.

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Claix, France

Simon Deleonibus