Cambridge Silicon Radio Limited

Qualcomm Technologies International, Ltd.

Simon Chang

Terence Chi-Fung Kwok

Rainer Herberholz

Erik David Lindskog

Alexander Thoukydides

James Digby Yarlet Collier

Timothy John Newton

Hong Wan

Ian Michael Sabberton

Steve Jones

Paul Egan

Kwangseok Han

Philip Macphail

Marco Bruno

Stuart Aitken

There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Receiver and methods for calibration thereof

An integrated circuit includes a digital interface for connection to a host controller; an antenna connection for connection to an antenna; a radio frequency transceiver for communicating data in accordance with one or more radio communication protocols, the radio frequency transceiver being configured to communicate radio frequency signals over the antenna connection in response to data exchanged over the digital interface; and radio loop-through circuitry for exchanging radio frequency signals with another integrated circuit, the radio loop-through circuitry being configured to provide radio frequency signals received at the antenna connection to an output connection of the integrated circuit.

Loop-through circuit

A transceiver includes a first circuit having a connector for connection to an antenna and receiving circuitry, and a second circuit having transmitting circuitry. The first and second circuits are coupled using a balun, where the balun is arranged so that its unbalanced side is in the first circuit and its balanced side is in the second circuit.

Transmit/receive switch

An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes.

Power splitter and combiner

Apparatus for controlling the generation of a DC signal at the output of a mixer, so that the DC signal is predictable, enabling a static offset compensation voltage to offset the DC signal. The apparatus comprises a mixer configured to receive a first and a second input signal, the mixer being such as to generate a first DC signal at the output of the mixer when the first and second input signals have the same frequency and a first relative phase, a phase detector for determining the relative phase of the first and second signals, and a phase modifier configured to modify the phase of the second signal relative to the first signal in dependence on the determination of the relative phase between the first and second signals such that the resulting DC signal at the output of the mixer is the first DC signal.

Architecture to remove a bimodal dynamic DC offset in direct conversion receiver

A SRAM memory element comprises an influencing element which sets the state of the memory cells within the memory element on start-up to defined values. These defined values are set at the design stage such that on start-up the volatile memory contains firmware or other data. Dependent upon the implementation of the influencing element, the values of stored in the memory cells may be fixed or may subsequently be overwritten during operation of the device. The memory cell may comprise two cross-coupled inverters and the influencing element comprises at least one transistor arranged to connect the input to one of the inverters to ground or a power supply rail when voltage is applied to a controlling node of the transistor.

Memory design

An analog-to-digital converter comprising: first and second sets of ordered nodes, each first node having a corresponding second node; for each first node, a respective first resistor and current source pair, the resistor of each pair being connected to a first converter input and the current source of each pair being coupled to the respective first node; for each second node, a respective second resistor and current source pair, the resistor of each pair being connected to a second converter input and the current source of each pair being coupled to the respective second node; and a plurality of first comparators, each first comparator having its first input connected to a first node and its second input connected to the corresponding second node; wherein each of the first resistor and current source pairs are configured so as to provide an orderly progression of voltages at the first nodes and each of the second resistor and current source pairs are configured so as to provide an orderly progression of voltages at the second nodes.

High speed low voltage flash

An analog lo digital converter comprising: a first set comprising nodes defined by circuitry such that each node is at a respective voltage, the voltages on the nodes being in an orderly progression between the voltage of a first current source and the voltage of a first input node; a second set comprising nodes defined by circuitry such that each node is at a respective voltage, the voltages on the nodes being in an orderly progression between the voltage of a second current source and the voltage of a second input node; a plurality of comparators, each comparator being arranged to compare the voltage on a node in the first set with the voltage on a respective node in the second set; and a pair of switching devices arranged between the first current source and the first set of nodes, the first switching device of the pair connected so as to supply the current from the first current source to all said nodes in the first set, and the second switching device of the pair connected so as to supply the current from the first current source to a subset of said nodes in the first set which are closest in voltage to the voltage of the first input node.

Rail to rail flash

A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of current is dependent on the voltage applied to the control node, wherein each row has a word line connected to the control nodes of the switches of that row, each column comprises only one switch from each row, and each column has first, second and third bit lines connectable to one of the switched nodes of each switch of that column to define the stored data, the method comprising: fixing the voltage of the second bit line of the switch and reading data from the first and third bit lines, and subsequently: fixing the voltage of the first bit line of the switch and reading data from the second and third bit lines.

Method for reading ROM cell

A mixer comprising a pair of low frequency mixer inputs, a pair of high frequency mixer inputs, a pair of mixer outputs, four switching units, each switching unit comprising a low frequency switching unit input, a high frequency switching unit input, a switching unit output, a node connected via a high pass filter to the respective high frequency switching unit input and via a low pass filter to the respective low frequency switching unit input and a switching device arranged to provide an output at the respective switching unit output in dependence on the voltage at the respective node, and comprising a first feedback loop responsive to the voltage at the first low frequency mixer input and arranged to regulate the current through the outputs of the first and second ones of the switching units so that the total current through the outputs of the first and second ones of the switching units is substantially proportional to the voltage at the first low frequency mixer input and a second feedback loop responsive to the voltage at the second low frequency mixer input and arranged to regulate the current through the outputs of the third and fourth ones of the switching units so that the total current through the outputs of the third and fourth ones of the switching units is substantially proportional to the voltage at the second low frequency mixer input.

Growing community of inventors

Cambridge, United Kingdom

Simon Chang