Intel Corporation

Hewlett-packard Development Company, L.p.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Other

Hewlett-packard Company

Simon C Steely, Jr

Stephen R Van Doren

Gregory Edward Tierney

Kent D Glossop

Kermin Elliott Fleming, Jr

William C Hasenplaugh

Madhumitra Sharma

Samantika S Sury

Joel S Emer

David J Sager

Kourosh Gharachorloo

Aamer Jaleel

Stephen R VanDoren

Benjamin Keen

Robert Valentine

Mark Jay Charney

Edward Thomas Grochowski

Richard J Dischler

Asit K Mishra

William J Butera

Kermin ChoFleming

Samantika Subramaniam

Robert G Blankenship

Dennis Ryan Bradford

Peter J Bannon

Richard B Gillett, Jr

Raj K Ramanujan

Yongzhi Zhang

David Bach

Christian Karl

Barry Tannenbaum

Olivier Franza

Brian Leung

James B Keller

Tryggve Fossum

Edward J McLellan

Chris J Newburn

Robert E Stewart

Fabrizio Petrini

David B Fite, Jr

Mitchell Diamond

Joseph Dominic Macri

Glenn P Garvey

Jinjie Tang

Jim Sukha

Jesus Corbal

Alan G Gara

Ravishankar Iyer

George Zacharias Chrysos

Li Zhao

Paul Caprioli

David Martin Fenwick

Donald K Newell

Srihari Makineni

Pratik M Marolia

Malini Krishnan Bhandaru

Ramesh Kumar Illikkal

Michael C Adler

Yu Bai

Eric R Borch

Ping Tak Peter Tang

John H Zurawski

David Curtis Ives

Chinmay Ashok

Chester W Pawlowski

Craig Durand Keefer

Uma Srinivasan

Kermin E ChoFleming, Jr

Daniel Towner

Rohan Sharma

William B Noyce

Neal C Crago

Walter A Beach

David A Webb

David K Miller

Chiachen Chou

Chuanjun Zhang

Hari Krishnan Nagpal

David W Davis

Louise Huot

Scott McFarling

Swapna Raj

Carole-Jean Wu

St Phen R Van Doren

Madhu Sharna

Nikolaos Hardavellas

A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.

Techniques for near data acceleration for a multi-core architecture

Systems, methods, and apparatuses relating to a sign modification field for fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.

Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator

Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Layered super-reticle computing : architectures and methods

Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Apparatuses, methods, and systems for operations in a configurable spatial accelerator

Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.

Signal pathways in multi-tile processors

Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

Processors, methods, and systems for debugging a configurable spatial accelerator

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Systems, methods, and apparatuses relating to memory interface circuit allocation in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for an improved memory sub-system design via the improvements to allocation discussed herein.

Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator

Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

Switchable topology processor tile and computing machine

Growing community of inventors

Hudson, NH, United States of America

Simon C Steely, Jr