Qualcomm Incorporated

Simon Booth

Serag Gadelrab

Moinul H Khan

Vinod Chamarty

Milivoje M Aleksic

Bohuslav Rychlik

Stephen A Molloy

Chinchuan Andrew Chiu

Meghal Varia

Jeffrey Gemar

Boris Andreev

Tauseef Kazi

Kyle Ernewein

Aravind Bhaskara

Olivier Alavoine

Tom Longo

Tao Shen

Edoardo Regini

Wenbiao Wang

Renatas Jakushokas

Sejoong Lee

Saurabh Patodia

Christopher E Koob

Mark Michael Schaffer

Jaya Prakash Subramaniam Ganasan

George Patsilaras

Feng Wang

Anwar Q Rohillah

Joshua Stubbs

Haw-Jing Lo

Aris Balatsos

Michael Hawjing Lo

King-Chung Lai

Sean Sweeney

Cristian Duroiu

Robert Nicholson Gibson

Kris Tiri

Johnny Jone Wai Kuan

Myil Ramkumar

Bhupinder Singh Pabla

Milivoje Aleksic

Serag Monier Gadelrab

Christopher Edward Koob

Sean David Sweeney

Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Forced idling of memory subsystems

An exemplary method for intelligent compression defines a threshold value for a temperature reading generated by a temperature sensor. Data blocks received into the compression module are compressed according to either a first mode or a second mode, the selection of which is determined based on a comparison of the active level for the temperature reading to the defined threshold value. The first compression mode may be associated with a lossless compression algorithm while the second compression mode is associated with a lossy compression algorithm. Or, both the first compression mode and the second compression mode may be associated with a lossless compression algorithm, however, for the first compression mode the received data blocks are produced at a default high quality level setting while for the second compression mode the received data blocks are produced at a reduced quality level setting.

System and method for intelligent data/frame compression in a system on a chip

An exemplary method for intelligent compression defines a threshold value for a key performance indicator. Based on the key performance indicator value, data blocks generated by a producer component may be scaled down to reduce power and/or bandwidth consumption when being compressed according to a lossless compression module. The compressed data blocks are then stored in a memory component along with metadata that signals the scaling factor used prior to compression. Consumer components later retrieving the compressed data blocks from the memory component may decompress the data blocks and upscale, if required, based on the scaling factor signaled by the metadata.

Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

Bandwidth/resource management for multithreaded processors

Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

System and method for uniform interleaving of data across a multiple-channel memory architecture with asymmetric storage capacity

Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Arbitrating bus transactions on a communications bus based on bus device health information and related power management

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San Diego, CA, United States of America

Simon Booth