Advanced Risc Machines Limited

Simon Anthony Segars

A data processing apparatus comprising an integrated circuit having a processor core surrounded by a scan chain is described. The processor core can execute program instructions using either a system clock signal MClk or a test clock signal DClk. A clock selecting bit S within the program instructions for test operation indicates which clock is to be used and a clock selecting mechanism selects the indicated clock signal and passes this to the processor core When the system clock MClk is selected execution of the program instruction by the processor core may be coordinated with the operation of connected auxiliary circuits such as a DRAM

Data processing apparatus and testing method

An integrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the integrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is reused to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation.

Integrated circuit test controller

An integrated circuit test mechanism based upon the JTAG standard utilises serial scan chains for applying signals to and capturing signals from predetermined nodes within an integrated circuit (2). Multiple independent scan chains (12, 14, 16) are provided for different circuit units (4, 6, 8, 10) within the integrated circuit, i.e. individual scan chains (12, 14) for circuit elements such as a central processing core (4) or a cache memory (8). The scan chain controller (18) is responsive to a scan chain selecting instruction (Scan-N) received at its serial input (20) to capture a scan chain specifying value at the serial input. The scan chain specifying value is then used to control the position of a scan chain multiplexer (28) that selects one of the multiple scan chains to which subsequent instructions received at the serial input are applied.

Integrated circuit test mechansim and method

An integrated circuit is described having a scan chain of the JTAG type in which there are provided a plurality of serially connected test cells 2. The test cells serve the additional function of operating during the normal operation of the integrated circuit to store signal values that are logically combined (compared) with signal values generated by the integrated circuit to yield control signals into for controlling the operation of the integrated circuit. This allows the storage capacity of the test cells to be utilised during normal operation when they would otherwise be idle.

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Cambridge, United Kingdom

Simon Anthony Segars