Arm Limited

Simon Andrew Ford

Dominic Hugo Symes

Andrew Christopher Rose

Alastair David Reid

David James Seal

David Raymond Lutz

Christopher Neal Hinds

Edmund Thomas Grimley-Evans

Christopher James Styles

Stuart David Biles

Antony John Penton

Wilco Dijkstra

Simon John Craske

David Michael Bull

John Michael Horley

Alex James Waugh

Emre Özer

Stephen John Hill

Sean Tristram Ellis

Daryl Wayne Bradley

Paul Stanley Hughes

Lionel Belnet

Stephane Eric Sebastien Brochier

Edward Charles Plowman

Katherine Elizabeth Kneebone

George James Milne

Richard York

Paul Matthew Carpenter

Paul Halliday Peeling

A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry.

Data processing on a non-volatile mass storage device

A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Method and apparatus for tuning a processor to improve its performance

A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.

Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number

A data processing apparatus and methods are disclosed. The data processing apparatus comprises: data processing elements operable to process data; an energy management unit operable to generate energy management information indicative of an energy state of at least one of the data processing elements when processing said data; and logic operable to receive said energy management information and to generate energy management information items associating said energy state with the processing of said data. The information items can provide visibility of how the Energy State of the data processing elements vary in response to the processing of data. Providing this visibility of the Energy State can advantageously enable more detailed the energy management to be performed and the Energy State of the data processing elements to be optimized.

Energy management system configured to generate energy management information indicative of an energy state of processing elements

A shared memory is provided accessible by a central processing unit and a graphics processing unit. A bus is provided via which the central processing unit, graphics processing unit and shared memory communicate. A first mechanism controls the graphics processing unit and the central processing unit routes control signals via the bus. An interface is provided between the central processing unit and the graphics processing unit, and an additional mechanism controls the graphics processing unit and the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, and it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.

Apparatus and method for communicating between a central processing unit and a graphics processing unit

A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

Error correction in a set associative storage device

A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults.

Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations

A computer implemented tool is provided for assisting in the mapping of a computer program to a data processing apparatus wherein multiple physical instances of a logical variable in the computer program are required. A computer program is provided as the input to the tool which analyses the data flow of the program and identifies multiple physical instance requirement for logical variables. The tool adds mapping support commands, such as instantiation commands, Direct Memory Access (DMA) move commands and the like as necessary to support the mapping of the computer program to a data processing apparatus.

Variable coherency support when mapping a computer program to a data processing apparatus

A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatusincorporating an asymmetric memory hierarchy formed of a plurality of memories. An at least partial architectural descriptionis provided as an input variable to the tool and used to infer missing annotations within a source computer program, such as which functions are to be executed by which execution mechanismsand which variables are to be stored within which memories. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus

Mapping a computer program to an asymmetric multiprocessing apparatus

An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.

Monitoring values of signals within an integrated circuit

The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model, when executing, to output one or more features identifying execution behavior of the component model. A statistical model is then arranged to receive the one or more features output by the component model, and to generate the output dependent on one or more features. The component model may not explicitly model features that can be used to effectively predict values of the observable property, features that a statistical model depends on may still be captured in the underlying logic and implementation of the component model. By extracting features identifying execution behavior of the component model, this can provide a suitable input to the statistical model.

System and method for modelling a hardware component of a data processing apparatus

Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.

Managing cache coherency in a data processing apparatus

Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer 'n' of the groups of data elements over a corresponding 'n' processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the &#x2018;n&#x2019; of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages. By forwarding the data elements to fill the bubble an improved throughput can be achieved and since a constant stream of data can be transformed without the need to increase the number of input or output registers required to support the permute logic, the need to duplicate the permute logic or the need to introduce any additional storage elements.

Data processing apparatus

A register data storeis provided within a data processing system. The register data storemay be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S, Sfor the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store

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Cambridge, United Kingdom

Simon Andrew Ford