Motorola Corporation

Motorola Solutions, Inc.

Arris Enterprises LLC

Silviu Chiricescu

Ali Saidi

Philip E May

Kent Donald Moat

Raymond Brooke Essick, Iv

James M Norris

Brian Geoffrey Lucas

Michael Allen Schuette

Venugopal Vasudevan

Loren J Rittle

Nitya Narasimhan

Joseph F Wodka

Yang Yu

Brian Jeffrey Lucas

Kent D Moat

The present invention monitors a user's activities to determine how much attention he is paying to one or more devices. Based on the information gathered about the user's current 'attention profile,' a 'user-interaction parameter' is set that reflects where the user's attention is focused and, ideally, how much of his attention is given to each device. Then, based on the user-interaction parameter, the user interface of at least one of the user's devices is configured to optimize the user's interactions, given the amount of attention he is currently giving to this user interface. If the user is giving the majority of his attention to the television, for example, then the user interface of a companion device can be configured to emphasize the types of interactions available to a user who is not actively watching the companion device.

Supporting multiple attention-based, user-interaction modes

A method and apparatus for allocating resources to a node in an ad-hoc communication system is provided herein. During operation, nodes of the system will receive resource allocations from their parent node. The resource allocation comprises a portion of available resources that may vary in size. Each node will determine the resource needs for its children nodes only and then dynamically assign resources to them. The resources assigned to the children nodes comprise a portion of the resources assigned to the node by its parent node. Additionally, knowledge as to how the children further allocate resources to their own children is not known by the parent, however, the children nodes must allocate a portion of their resource to their children nodes.

Method and apparatus for resource allocation

A method and apparatus to facilitate managing communications with at least one wireless node () having an outbound payload memory in a severely resource-constrained wireless network () can provide for a coordinator node () for that network providing () information regarding remaining capacity of those outbound payload memories and then automatically using () that information in integral combination with a bandwidth allocation management process to control allocation of at least one wireless communication resource by which the wireless nodes can transmit items contained in the outbound payload memory.

Method and apparatus to facilitate bandwidth allocation management in integral combination with memory capacity information

A method and apparatus that allocates bandwidth among wireless sensor nodes in a wireless sensor network (WSN) is disclosed. The method may include allocating transmission time slots for a plurality of wireless sensor nodes based on at least one channel quality metric, determining battery levels in each of the plurality of wireless sensor nodes and average battery level of all of the plurality of wireless sensor nodes, determining differences in battery level between each of the plurality of wireless sensor nodes and average battery level of all of the plurality of wireless sensor nodes, wherein if any such difference is above a predetermined threshold, increasing the transmission time slots allocation of wireless sensor nodes having higher battery levels relative to other wireless sensor nodes in the plurality of wireless sensor nodes.

Method and apparatus for battery-aware dynamic bandwidth allocation for wireless sensor networks

A method and apparatus that allocates bandwidth among wireless sensor nodes in wireless sensor groups in a wireless sensor network (WSN) is disclosed. The method may include forming a plurality of wireless sensor node groups from a plurality of wireless sensor nodes based on battery levels of the wireless senor nodes, allocating transmission time slots for the wireless sensor nodes in each of the wireless sensor node groups based on at least one channel quality metric, determining average battery levels for each of the wireless sensor node groups and average battery level of all of the wireless sensor nodes, determining differences between the average battery levels of each of the wireless sensor node groups and the average battery level of all of the wireless sensor nodes, wherein if any difference in the average battery levels is above a predetermined threshold, regrouping the plurality of wireless sensor nodes according to the battery levels of the plurality wireless sensor nodes to minimize any variance in average battery level across all of the wireless sensor node groups.

Method and apparatus for battery-aware dynamic bandwidth allocation for groups of wireless sensor nodes in a wireless sensor network

A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

Streaming vector processor with reconfigurable interconnection switch

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Scheduler of program instructions for streaming vector processor having interconnected functional units

A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Method of programming linear graphs for streaming vector computation

An interconnection device () with a number of links (and), each link having a number of link input ports (), link output ports () and storage registers (). An input selection switch () is coupled to a selected link input port to receive an input data token. The storage registers () may be used to store input data tokens. A storage access switch () is coupled to the input selection switch () and to the storage registers () and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch () receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

Interconnection device with integrated storage

A memory interface device ( ) providing a fractional address interface between a data processor ( ) and a memory system ( ) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator ( ) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit ( ) coupled to the address generator ( ) for retrieving first and second data values from the memory system ( ) at the first and second memory addresses, respectively. The device also includes a data access unit ( ) for interpolating between the first and second data values and passing the interpolated value to the data processor ( ). The memory interface has application in a variety of data processing systems, including digital signal processors and streaming vector processors.

Growing community of inventors

Chicago, IL, United States of America

Silviu Chiricescu