Alcatel

Telettra Telefonia Elettronica E Radio Spa

Alcatel Lucent

Alcatel N.v.

Alcatel Italia S.p.a.

Xilinx, Inc.

Alcaltel

Telettra-telefonia Elettronica

Telettra-telefonia Elettronica E Radio S.p.a. Corso Buenos Aires

Telettra - Telefonia Elettronica E Radio

Silvio Cucchi

Carlo Costantini

Ludovic Noirie

Luca Gabriele Razzetti

Paolo Rossi

Luigi Ronchetti

Georg Post

Alberto Lometti

Silvano Frigerio

Stefano Gastaldello

Fabio Valente

Giulio Gladiali

Marisa Treu

Paolo Novellini

Riccardo Gemelli

Marzio Orsucci

Marco Lenti

Marco Modena

Noriaki Kaneda

Andreas Leven

Alberto Bellato

Vincenzo Sestito

Marzio Barbero

Giorgio Parladori

Marco Fratti

Sonia Rinaldi

Claudio Colombo

Stefan Weisser

Primo Garofoli

Giovanni Guasti

Paolo Sorge

Hans-Jörg Jäkel

Giuseppe Badalucco

Sergio Cabrini

Francesco Molo

Stefano Carbone

Gianfranco Cariolaro

Maurizio Lazzer

Paolo Zapparoli

Carlo Constantini

Roberto Peruta

Giovanna Vecchietti

Vittorio Corradi

Michele Marchiori

Cristian Perissinotto

Daniele Meli

Marco Andreasi

Gianluca Macheda

Luca Cenzato

Luigi Ronchette

It is disclosed an optical coherent receiver for an optical communication network. The optical coherent receiver is configured to receive a modulated optical signal and to process it for generating an in-phase component and a quadrature component. The optical coherent receiver comprises a power adjuster in turn comprising a multiplying unit and a retroactively connected digital circuit. The multiplying unit is configured to multiply the in-phase and quadrature components by in-phase and quadrature gains, respectively, thereby providing power-adjusted in-phase and quadrature components. The digital circuit is configured to compute: a common gain indicative of a sum of the powers of the power-adjusted in-phase and quadrature components; a differential gain indicative of a difference between the powers of the power-adjusted in-phase and quadrature components; and the in-phase and quadrature gains as a product and a ratio, respectively, between the common gain and the differential gain.

Power adjustment of in-phase and quadrature components at a coherent optical receiver

A multi-service transport apparatus for integrated transport networks that may have an electrical matrix, termination function means handling signals incoming at said apparatus input, a plurality of termination function means interfacing different layers, and adaptation function means. The termination function means handling incoming signals are implemented in input/output port devices; the termination function means interfacing different layers and said adaptation function means are implemented in adapter devices. The matrix performs exclusively the switching of the incoming signals that are already terminated and adapted by said input/output port devices and by said adapter devices and it is transparent with respect to the signal format. The switch may have a time division multiplexing matrix provided with a number of matrix inputs and a number of matrix outputs; source address generators, connected to matrix outputs of the time division multiplexing matrix.

Multi-service transport apparatus with switch for integrated transport networks

There is described a method for transmitting N parallel data flows on a parallel bus. The method comprises, at a first communication device: generating a further parallel data flow comprising alignment words periodically distributed with a period; at each period, rotating the N of parallel data flows and the further parallel data flow thus generating N+1 rotated parallel data flows, each comprising part of the alignment words periodically distributed with a frame period; transmitting the N+1 rotated parallel data flows on respective physical connections of the parallel bus. The method further comprises, at a second communication device: aligning the N+1 rotated parallel data flows by using the alignment words, thus compensating skew and obtaining N+1 aligned parallel data flows; and at each period, de-rotating the N+1 aligned parallel data flows, thus generating N de-rotated parallel data flows corresponding to the N parallel data flows.

Transmission of parallel data flows on a parallel bus

Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M-M, E-E) is achieved by slicing an input signal into k parallel signal slices (x()-x()) with k&#x3e;2; coding the k signal slices into a number of n coded signal slices (x()-x()) with n&#x3e;k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB-MB, EB, EB), each carrying a second number of matrix modules (M-M, E-E). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Equipment protection method and apparatus

Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

Clock generation using a fractional phase detector

A method for performing an iterative n-dimensional decoding of a data structure comprising a data bit frame. The method includes receiving possibly errored data; computing syndromes in all the n dimensions in a single step; storing the first calculated syndromes; processing syndromes in a first dimension; correcting errors; and updating the syndromes which have been affected by the correction in the first dimension; and processing syndromes in all the possible dimensions up to the n-th one and, for each of the processed syndromes, correcting errors and updating the syndromes in all the dimensions which have been affected by the correction. The time required by each sub-iteration (from second sub-iteration on) will be progressively reduced. The number of iterations is increased without increasing the delay and processing complexity.

Iterative n-dimensional decoding

Disclosed is a device and method for processing a frame including overhead and payload, the device comprising: a first hardware module for processing the payload, the payload processing comprising termination/adaptation and cross-connection functions; and a second hardware module for processing at least a part of overhead, wherein said second hardware module cooperates with the first hardware module for controlling the payload cross-connection and consequent actions.

Hardware functional partitioning in a system platform of a telecommunication network element

The present invention provides for a method and apparatus for carrying out connection and related input/output processing functions in a Sinchronous Digital Hierarchy (SDH/SONET) transport node (network), in which the payload switching matrices (e.g. MSPC and HPC matrices for an High Order VC system) collapse into one single functional block (MTRX), while the Virtual Container (VCs) monitoring functions (HVC_RX, HVC_TX) are shifted to the Input/Output position of the matrices.

Method and apparatus for carrying out connection and related input/output processing functions in a synchronous digital hierarchy transport node

To selectively route stand-by packets in input modules to destination output modules via a switching matrix, distributed arbitration functions are executable by successive arbitration cycles. Each cycle comprises: a first phase executable by each input controller to send each output controller requests representative of the quantities of required stand-by packets; a second phase executable by each output controller to determine the quantity of admissible packets depending on the requests; a third phase executable by a central arbitration unit to determine allowed aggregate quantities depending on all the admissible quantities; and a fourth phase executable by each input controller to determine the allowed packet quantities depending on the admissible quantities and of the allowed aggregate quantities.

Packet-switched system for communication network node

Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Time division multiplexed link connections between a switching matrix and a port in a network element

In order to switch selectively via a packets switching matrix waiting in the input modules (IMi) to address output modules, an arbitration function (CSC) selects by successive cycles, from all the pairs of input and output modules, separate subsets. Each cycle comprises p successive phases (x) associated respectively to p arbitration functions. Processing units (PUi) each execute the p functions, each function acting on three parameters termed 'residual required quantity', 'input capacity' and &#x201c;output capacity&#x201d;, the values of which are related to a single pair and are set at the start of the cycle. Each phase consists of N successive steps (y) associated respectively to said subsets, each step being executed in parallel by the processing units (PUi) in order to calculate by means of the arbitration functions the &#x201c;partial&#x201d; accepted quantity values and to reset the parameters for the next step. Application to telecommunication networks, particularly multiservice.

Packets switching system for telecommunications network node

Disclosed is a memory-based switching matrix for cross-connecting the content of a plurality of input flows into the content of a plurality of output flows, the input flows being in the form of frames and said content being Time Division Multiplexed or packet data or whatever, the matrix comprising a number of physical memories for memorizing incoming input flows to be output in a predesigned order. The matrix is characterized in that the number of physical memories comprises a first number of memories having a writing role and a second number of memories having a reading role, with the second number being higher than the first number, and in that the role of each memory changes after at least one clock cycle. The arrangement according to the invention saves a number of physical memories with respect to known arrangements.

Switching matrix for a telecommunication network element

Described is a method and apparatus for mapping Fast Ethernet data interfaces (in addition to possible data interfaces of different type) into a single VC-4 Virtual Container of a STM-1/OC-3 payload transmitted to a radio-link system. The method is characterized by the steps of: packeting the Fast Ethernet signal and any other signal, mapping the packets into a single (VC-4) Virtual Container of a STM-1/OC-3 payload of a SDH/SONET signal frame, and transmitting said signal frame through the point-to-point radio-link, said radio link being a point-to-point SDH/SONET radio link. All the packets have the same format and are associated to a header for identifying the source. The interfaces of different type are conveniently grouped. Possibly, the VC-4 is filled with null packets to exhaust the maximum available capacity.

Method and apparatus for mapping fast ethernet data interfaces into a single VC-4 virtual container of a STM-1/OC-3 payload transmitted in a radio-link system

The switching system includes input modules (IM, IM, IMi, IMn) each connected to a switching matrix () and to a corresponding controller (). Each input module (IMi) organizes packets that it receives into digital data blocks with a fixed size, and makes transfers of these blocks by successive cycles to the matrix (). Each of these blocks is organized into groups of digital data, these groups having corresponding modifiable sizes and being stored according to a predetermined order and associated with the corresponding output ports (OP, OP, OPj, OPn) in the system. Each of these groups is formed of packets to be sent to a single corresponding output port. Any block transfer to the matrix () is accompanied by transmission of information representative of the corresponding sizes of the groups of the transferred block to the said controller (), and the groups of each transferred block are switched to their corresponding destination output ports as a function of this information representing the sizes. This system makes it possible to satisfy service quality criteria applicable to switched packets, while limiting the quantity of data to be exchanged between the input modules and the controller. To be applied to telecommunication networks, particularly multiservice networks.

Packet switching system for a communication network node

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Gaggiano, Italy

Silvio Cucchi