International Business Machines Corporation

Silvia Melitta Mueller

Steven R Carlough

Petra Leber

Klaus Michael Kroener

Cedric Lichtenau

Maarten Jakob Boersma

Kerstin Claudia Schelm

Michael Klein

Michael Klaus Kroener

Andreas Wagner

Sang Hoo Dhong

Hwa-Joon Oh

Reid T Copeland

Christophe J Layer

Jonathan D Bradbury

Jochen Preiss

Juergen Haess

Son Trong Dao

Kailash Gopalakrishnan

Ankur Agrawal

Eric M Schwarz

Bruce Martin Fleischer

Christian Jacobi

Brian William Thompto

Markus Kaltenbach

Jose Eduardo Moreira

Brett Olsson

Jungwook Choi

Erez Barak

Xin Guo

Son Dao Trong

Eyal Gonen

Manuela Niekisch

Tina Babinsky

Timothy John Slegel

Balaram Sinharoy

Harm Peter Hofstee

Naigang Wang

Harry S Barowski

Adam B Collura

Mauricio J Serrano

Daniel Lipetz

James Raymond Cuffney

Cédric Lichtenau

Kevin Duc Tran

Hiroo Nishikawa

Dung Q Nguyen

Hung Qui Le

Phil C Yeh

Jens Peter Seifert

Brad William Michael

Jens Leenstra

Tim Niggemeier

Stefan Payer

Debapriya Chatterjee

Sunil K Shukla

Niels Fricke

Michael F Cowlishaw

Razvan Peter Figuli

Nicol Hofmann

Jörg-Stephan Vogt

Jinwook Oh

J Adam Butts

Dongsoo Lee

Martijn Diede Berkers

Sourabh Chougule

Manoj Kumar

Pavankrishna Ellore Ramesh

L'Emir Salim Chehab

Markus Lachenmayr

Reid Copeland

Steven Carlough

Michael K Gschwind

Giles R Frazier

Joel Abraham Silberman

Stephen Victor Kosonocky

Vijayalakshmi Srinivasan

Xiao Lin Sun

Ulrich Mayer

Kattamuri Ekanadham

Thomas Winters Fox

Gordon Clyde Fossum

Daniel Brand

Gal Ashour

Holger Wetter

Mingu Kang

Udo Krautz

Michal Rimon

Oz Dov Hershkovitz

Karen Holtz

Avishai Moshe Fedida

Maarten Jokob Boersma

K Michael Kroener

Revital Arieli

Eric Mark Schwarz

Eric Schwarz

Michael Frederic Cowlishaw

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Hardware-based implementation of secure hash algorithms

A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Hardware-based message block padding for hash algorithms

Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be 'don't care' terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.

Enhanced low precision binary floating-point formatting

Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Compute array of a processor with mixed-precision numerical linear algebra support

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Instruction handling for accumulation of register results in a microprocessor

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Vector convert hexadecimal floating point to scaled decimal instruction

In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.

Hybrid floating point representation for deep learning acceleration

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Condition code anticipator for hexadecimal floating point

Embodiments for implementing a fused multiply-multiply-accumulate ('FMMA') unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.

Ultra-low precision floating-point fused multiply-accumulate unit

An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Decimal scale and convert and split to hexadecimal floating point instruction

A reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture includes reduced precision execution units with a majority of the execution units operating at reduced precision and a minority of the execution units are capable of operating at higher precision. The execution units operate in parallel within a programmable execution element to share instruction fetch, decode, and issue pipelines and operate on the same instruction in lock-step to minimize instruction-related overhead.

Reduced precision based programmable and SIMD dataflow architecture

Methods and systems for division operation are described. A processor can initialize an estimated quotient between the dividend and the divisor separately from a floating-point unit (FPU) pipeline. The processor can implement the FPU pipeline to execute a refinement process that can include at least a first iteration of operations and a second iteration of operations. The refinement process can include, in the first iteration of operations, generating a first unnormalized floating-point value using the initialized estimated quotient. The refinement process can include, in the second iteration of operations, generating a second unnormalized floating-point value using the first unnormalized floating-point value. The processor can determine a final quotient based on the second unnormalized floating-point value.

Low latency floating-point division operations

An example computer-implemented method includes receiving a first value, a second value, a third value, and a fourth value, wherein the first value, the second value, the third value, and the fourth value are 16-bit or smaller precision floating-point numbers. The method further includes multiplying the first value and the second value to generate a first product, wherein the first product is a 32-bit floating-point number. The method further includes multiplying the third value and the fourth value to generate a second product, wherein the second product is a 32-bit floating-point number. The method further includes summing the first product and the second product to generate a summed value, wherein the summed value is a 32-bit floating-point number. The method further includes adding the summed value to an addend value to generate a result value, wherein the addend value and the result value are 32-bit floating-point numbers.

Mixed precision floating-point multiply-add operation

Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

Parallel rounding for conversion from binary floating point to binary coded decimal

Various embodiments are provided for facilitating data processing by one or more processors in a computing system. An instruction to be executed may be obtained. The instruction is a single instruction multiple data (SIMD) reduction operation of an operand vector with a plurality of vector elements. The SIMD reduction operation may be executed to produce a result vector with a plurality of alternative vector elements. One or more reduction functions may be performed on each of a pair of vector elements from the plurality of vector elements of the operand vector and a result of the one or more reduction functions may be placed in a corresponding vector element of the result vector.

Facilitating data processing using SIMD reduction operations across SIMD lanes

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Altdorf, Germany

Silvia Melitta Mueller