University of California

Silvia H Chan

Umesh Kumar Mishra

Stacia Keller

Jeonghee Kim

Srabanti Chowdhury

Chirag Gupta

Ramya Yeluri

Matthew A Laurent

Xiang Liu

Jing Lu

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Metalorganic chemical vapor deposition of oxide dielectrics on N-polar III-nitride semiconductors with high interface quality and tunable fixed interface charge

Growing community of inventors

Santa Barbara, CA, United States of America

Silvia H Chan