Ford Motor Company Limited

Lsi Logic Corporation

Lsi Corporation

Silvia E Jaeckel

Brian A Day

Martin G Gravenstein

Michael A Vigil

Patrick R Bashford

The present invention is directed to a system and method for emulating a serial small computer system interface (SAS) connection for direct attached serial advanced technology attachment (SATA) communication are disclosed. A system in accordance with the present invention includes a host controller. The host controller includes a physical interface for accepting at least one of a SAS connection or a direct attached SATA device. A common interface logic configured to receive SAS communications and SATA communications having a SAS emulated connection is included in the host controller. An emulation logic is communicatively coupled to the common interface logic. The emulation logic being configured to determine a value of a ConnectedSata signal based on the state of a SATA link state machine.

Serial attached small computer system interface (SAS) connection emulation for direct attached serial advanced technology attachment (SATA)

Methods and structures for managing connection requests within a SAS controller operating as an initiator device. A SAS initiator device maintains a table of information regarding known SAS devices in the SAS domain. An index value is used by each of a plurality of link layer processing elements in the SAS controller to access information in the table. The index value is fewer bits than the complete eight byte SAS address and the logic to manipulate and compare the index value is therefore simpler than that required to directly manipulate a full SAS address. Further, the information table is shared by each of the link layer processing elements to further reduce complexity from replication of circuits and logic in the SAS controller.

Systems and methods for initiator mode connection management in SAS connections

Methods and structures for managing connection requests within a SAS controller operating as a target device. A SAS target device maintains a table of information regarding known SAS initiator devices in the SAS domain. An index value is supplied in transport layer requests and used by each of a plurality of link layer processing elements in the SAS controller to access information in the table. The index value is fewer bits than the complete eight byte SAS address and the logic to manipulate and compare the index value is therefore simpler than that required to directly manipulate a full SAS address. Further, the information table is shared by each of the link layer processing elements to further reduce complexity from replication of circuits and logic in the SAS controller.

Systems and methods for target mode connection management in SAS connections

A novel method and apparatus for encoding input data at a faster rate provides error detection, clock recovery, and reduction of spectral components near DC, and is capable of encoding data while embedding error detection information simultaneously. This encoding scheme may encode all input data in parallel while simultaneously embedding error detection information to quickly and properly encode input data.

Encoder with vector-calculated disparity logic

A data movement apparatus (10) and method therefor include a register file (14) for storing data in a plurality of addressable locations. A register decoder (18) is connected to the register file (14) to modify addresses to access desired data. During move commands, data is not physically moved in the register file (14), but the register decoder (18) modifies a variable upon receiving the move command to correlate the new logical address to the physical location.

Data movement apparatus and method

A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

Micro-sequencer apparatus and method of combination state machine and

A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.

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Colorado Springs, CO, United States of America

Silvia E Jaeckel