Micron Technology Incorporated

Other

Silvia Beltrami

Angelo Visconti

Kishore Kumar Muchherla

Seiichi Aritome

Violante Moschiano

Giovanni Campardo

Jeffrey S McNeil, Jr

Akira Goda

Ugo Russo

Mattia Robustelli

Niccolo' Righetti

Gian Pietro Vanalli

Massimo Ernesto Bertuccio

Stefano Corno

Laura Tatiana Czeppel

Alessandro Sottocornola Spinelli

Alexey Petrushin

Soojin Wi

Christian Monzio Compagnoni

Jonathan Scott Parry

A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

Selectively programming retired wordlines of a memory device

Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Programming selective word lines during an erase operation in a memory device

Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.

Programming of memory devices

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

Programming of memory devices in response to programming voltages indicative of programming efficiency

Programming of memory devices responsive to a stored representation of a programming voltage indicative of a programming efficiency

A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

Thermal treatment of flash memories

Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.

Limiting flash memory over programming

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

Reading memory cell history during program operation for adaptive programming

A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.

Methods for program verifying a memory cell and memory devices configured to perform the same

Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.

Methods to operate a memory cell

An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

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Almenno San Bartolomeo, Italy

Silvia Beltrami