Imec Vzw

Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Silvia Armini

Boon Teik Chan

Zheng Tao

Mikhail Krishtab

Mikhail Rodionovich Baklanov

Liesbeth Witters

Frederic Lazzarino

Annelies Delabie

Philippe Soussan

Christoph Adelmann

Steven Demuynck

Marc Schaekers

Rob Ameloot

Antony Premkumar Peter

Quoc Toan Le

Mikhaïl Baklanov

Ivo Stassen

Wenqi Zhang

Yiting Sun

Elisabeth Camerotto

Murad Redzheb

In a first aspect, the present disclosure relates to a method for forming a patterning mask over a layer to be patterned, the method comprising: (a) providing a first layer over a substrate, the substrate comprising the layer to be patterned, the first layer being capable to bond with a monolayer comprising a compound comprising a functional group for bonding to the first layer and a removable organic group, (b) bonding the monolayer to the first layer, (c) exposing the monolayer to an energy beam, thereby forming a pattern comprising a first area comprising the compound with the removable organic group and a second area comprising the compound not having the removable organic group, and (d) selectively depositing an amorphous carbon layer on top of the first area.

Resistless patterning mask

A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

Method for forming horizontal nanowires and devices manufactured thereof

Example embodiments relate to selective deposition of metal-organic frameworks. One embodiment includes a method of forming a low-k dielectric film selectively on exposed dielectric locations in a substrate. The method includes selectively depositing a metal-containing film, using an area-selective deposition process, on the exposed dielectric locations using one or more deposition cycles. The method also includes providing, at least once, a vapor of at least one organic ligand to the deposited metal-containing film resulting in a gas-phase chemical reaction thereby obtaining a metal-organic framework which is the low-k dielectric film. The low-k dielectric film has gaps on locations where no metal-containing film was deposited.

Selective deposition of metal-organic frameworks

The present disclosure relates to a method for selectively forming a dielectric material on a first area of a top surface of a substrate. In an embodiment, the method involves providing the substrate including the top surface, the top surface including the first area and a second area, the first area having a hydrophilicity characterized by a water contact angle of at least 45&#xb0; and the second area having a hydrophilicity characterized by a water contact angle of less than 40&#xb0;. The method also involves providing a precursor aqueous solution on the substrate, the precursor aqueous solution including: a solvent, a dielectric material precursor, a catalyst for forming a dielectric material from the dielectric material precursor, and an ionic surfactant. Further, the method involves removing the solvent.

Selective deposition of dielectric materials

A use of an amine-containing silane for forming a transition metal nitride is provided. In this use, the amine of the amine-containing silane is the source of at least some, preferably most and most preferably all of the nitrogen present in the transition metal nitride.

Formation of a transition metal nitride

A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

Method for forming a field effect transistor device having an electrical contact

Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.

Method for forming a vertical hetero-stack and a device including a vertical hetero-stack

The present disclosure relates to a method () for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing () a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX. X is selected from H, Cl, O&#x2014;CH, O&#x2014;CH, and O&#x2014;CH, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing () the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing () a layer on the III-V semiconductor surface in the non-oxidizing environment.

Layer deposition on III-V semiconductors

An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

Electroless metal deposition on a manganese or manganese nitride barrier

A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole exposing a metal surface and, optionally, an oxide surface. In one example, the method may include applying a self-assembled monolayer selectively on the exposed metal surface and/or on the oxide surface. The method may also include growing a metal on the self-assembled monolayer and on the exposed metal surface if no self-assembled monolayer is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal structure. The method may further include replacing the first sacrificial layer by a replacement dielectric layer having a dielectric constant of at most 3.9.

Metallization method for semiconductor structures

A method is provided for activating an exposed surface of a porous dielectric layer, the method comprising the steps of: filling with a first liquid at least the pores present in a part of the porous dielectric layer, the part comprising the exposed surface, removing the first liquid selectively from the surface, activating the exposed surface, and removing the first liquid from the bulk part of the porous dielectric layer.

Method for activating a porous layer surface

A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.

Method for self-assembly of substrates and devices obtained thereof

Polymer particles of improved mechanical hardness are provided, the polymer particles being subjected to a thermal cycle of heating and subsequently cooling. The polymer particles comprise combinations of preferably three monomers, the monomers having hydrophilic and hydrophobic groups in their polymer chain in order to achieve preferential orientation of the polymer chains in a polar solvent after applying the heating cycles of the invention (for example, but not limited to, polymethylmethacrylate and polystyrene based terpolymers and copolymers). Polymeric abrasives used in slurry compositions for polishing copper and their use in a chemical mechanical polishing method are also provided.

Polymer particles having improved mechanical properties and applications of same

A method for improving the mechanical hardness of polymer particles is provided, the method comprising subjecting the polymer particles to a thermal cycle of heating and subsequently cooling. The method is applicable for use with combinations of preferably three monomers, the monomers having hydrophilic and hydrophobic groups in their polymer chain in order to achieve preferential orientation of the polymer chains in a polar solvent after applying the heating cycles of the invention (for example, but not limited to, polymethylmethacrylate and polystyrene based terpolymers and copolymers). Polymeric abrasives used in slurry compositions for polishing copper and their use in a chemical mechanical polishing method are also provided.

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Heverlee, Belgium

Silvia Armini