Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Silvano Giorcelli

Giuseppe Giandonato

Carlo Demichelis

Valerio Barcaroli

Riccardo Cedolin

Giorgio Sofi

Giorgio Martinengo

Wolmer Chiarottino

Sergio Villone

A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

Modular signal-processing system

An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus--if the latter is available--whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.

Device for processing telephone signals, including a processor and a

Two substantially identical data processors, operating in parallel, include each a general-purpose computer and an associated data store connected to each other by way of a respective logic network, the two networks being substantially identical and intercommunicating for recurrent comparisons of their settings. Each network includes a buffer memory for the temporary inscription of addresses in the corresponding data store together with data words to be read out of and into that store at the inscribed addresses, as well as a pair of counters respectively keeping track of the successive operating cycles initiated by computer instructions and of the checks performed on the results of these operations. Detection of a disparity by a comparator in either network results in a regression of the cycle counter to a preceding cycle which checked out correctly, with reintroduction of an earlier word from the buffer memory into the data store if the cancelled operation involved a writing step.

System for checking two data processors operating in parallel

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Turin, Italy

Silvano Giorcelli