Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Silvano Appiano

Cesare Poggio

Paolo Destefanis

Gian B Alaria

Duccio Di Pino

An interface facilitating data transmission between a control processor, connected to an asynchronous two-way bus, and a plurality of terminals, connected to a common synchronous two-way bus, comprises a microprocessor responsive to periodically recurring access requests from the several terminals. The access requests are short pulses with a recurrence period greatly exceeding their duration, this period being nominally equal for all terminals and sufficient to accommodate one data transfer to or from each terminal with time remaining for execution of part of a main program performed by the control processor. Coinciding access requests from different terminals are handled according to a predetermined order of priority. The exchange of data takes place by way of a data memory and a buffer memory linked by an internal two-way bus. Data transfer between the control processor and a terminal takes place in three stages, i.e. between the processor and the buffer memory, between the buffer memory and the data memory, and between the data memory and the terminal. Except during the second stage, the processor has always access to the buffer memory.

Interface controlling bidirectional data transfer between a synchronous

An SS/TDMA communication system comprises a multiplicity of ground stations, including one master station and a number of traffic stations without control function, exchanging digitized voice or other message signals via a relay station aboard a satellite. Each ground station comprises base-band equipment including a transmitting section, a receiving section and a control unit. The control unit of the master station generates outgoing timing signals and processes incoming timing signals for synchronizing the operations of its own equipment and that of the traffic stations with the operation of a switching unit of the satellite-borne relay station; this control unit also emits routing instructions for that switching unit. The transmitting section of each ground station is served by an independent time base while its receiving section has a time base locked to the clock of the satellite; both time bases are adjustable by the associated control unit for correlation with the timing signals sent to and received back from the relay station.

Base-band equipment for ground stations of satellite telecommunication

A central processor controlling a set of peripheral units through an associated logic network is programmed to activate from time to time, through a direct connection by-passing the logic network, a checking unit including a read-only memory storing a variety of microprograms in areas individually addressable by the processor. Upon the reception of a memory address, a timing circuit is set to determine the frequency of stepping pulses advancing a counter which calls forth successive phases of the selected mircroprogram. Code words read out during these phases to the logic network are fed back by the latter to the processor for comparison with corresponding contents of its own program memory; in the event of a disparity, or when failure of the processor to emit a resetting signal lets the counter advance to the limit of its capacity, an alarm indicator is tripped.

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Montafia d'Asti, Italy

Silvano Appiano