International Business Machines Corporation

Silke Penth

Tobias Werner

Yuen H Chan

David Edward Schmitt

John D Davis

Paul Alan Bunce

Brian James Yavoich

Iris Maria Leefken

Harry S Barowski

Raphael C Polig

Michael B Kugel

Wolfgang Penth

Gerhard Hellner

Michael Stetter

Alexander Albert Woerner

A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.

Field-effect transistor placement optimization for improved leaf cell routability

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.

Layout of interconnect lines in integrated circuits

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical 'high' voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical 'low' voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

Managing semiconductor memory array leakage current

It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1&#x2266;i&#x2266;n&#x2212;1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th input; a first FET and a second FET in series configured for connecting the i-th column to a defined voltage level; wherein a first gate signal renders the first FET conductive, if the i-th column is not in conductive connection with the i-th input; wherein a second gate signal renders the second FET conductive, if the i-th column is not in conductive connection with the (i+1)-th input.

Memory circuit

An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.

Write address synchronization in 2 read/1write SRAM arrays

An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.

SRAM array comprising multiple cell cores

Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Defective memory column replacement with load isolation

A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.

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Holzgerlingen, Germany

Silke Penth