Samsung Electronics Co., Ltd.

Sihong Kim

Seungjun Bae

Su Yeon Doo

Hosung Song

Jaehyung Lee

Young-Hun Kim

Kwangil Park

JinGook Kim

Daehyun Chung

Jonghee Han

So-Young Lee

Byoung-Uk Yoon

Kyung-Soo Ha

Taeyoung Oh

Seung-Nyun Kim

Young-Hoon Son

Jung-Jae Lee

Taekyun Kim

Wu Seong Lee

Young-Chul Shin

A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

Semiconductor memory devices, memory systems including semiconductor memory devices, and operating methods of semiconductor memory devices

A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

Semiconductor memory device and detection clock pattern generating method thereof

A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

Semiconductor memory including pads arranged in parallel

An unmanned photographing device and method thereof is provided which includes establishing a wireless connection with an external electronic device using a communication device, receiving a first signal at a first three-dimensional (3D) position from the external electronic device through the wireless connection, the first signal comprising data associated with a first image comprising a first object, determining a second 3D position based on at least part of the data and the first 3D position, controlling the unmanned photographing device to fly to or near the second 3D position, tracking a second object corresponding to the first object using a camera, and capturing a second image comprising the second object at or near the second 3D position such that the second image corresponds to the first image.

Electronic apparatus and operating method thereof

Semiconductor memory device having detection clock patterns phase-inverted from each other and detection clock generating method thereof

A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed.

Integrated circuit memory devices including delayed clock inputs for input/output buffers and related systems and methods

An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A capacitor may be coupled to the amplifier output, and a buffer may be coupled to the capacitor so that the capacitor is coupled in series between the amplifier output and an input of the buffer with an output of the buffer being coupled to a buffered signal terminal. A variable resistive feedback circuit may be coupled between the input and output of the buffer with the variable resistive feed back circuit providing a variable resistance between the input and output of the buffer. A feedback resistance controller may be coupled to the variable resistive feedback circuit with the feedback resistance controller being configured to select a first resistance for the variable resistive feedback circuit for a first frequency of the input signal and to select a second resistance for the variable resistive feedback circuit for a second frequency of the input signal different than the first frequency with the first and second resistances being different.

AC coupling circuits including resistive feedback and related methods and devices

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Yongin-si, South Korea

Sihong Kim