Altera Corporation

Siew Ling Yeoh

Chin Hai Ang

Tze Sin Tan

Ala-Uddin Ismail

Kar Keng Chua

Jayabrata Ghosh Dastidar

Jun Pin Tan

Yee Liang Tan

Sze Yin Lee

Chiew Khiang Kuit

Arul Paniandi

Chong Tean Chuah

Kok Sun Chia

Yun Hui Moh

A method for generating configuration information using a computer aided design (CAD) tool includes a step to receive an intellectual property block. The method also includes a step to receive a configuration and status register (CSR) data file. The configuration and status register data file includes a user selected portion of runtime features from all of the available runtime features of the intellectual property block. The method may also include a step to receive an additional intellectual property block and an additional configuration and status register data file. Based on the two intellectual property blocks and the configuration and status register data files, a consolidated configuration and status register block may be formed. These intellectual property block(s) and configuration status register block(s) are formed on an integrated circuit device.

Intellectual property (IP) blocks with customizable configuration status register (CSR) circuitry

Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.

Integrated circuit with configurable test pins

An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Techniques for testing memory circuits

Growing community of inventors

Georgetown, Malaysia

Siew Ling Yeoh