Infineon Technologies Ag

Siegmar Köppe

Stephan Henzler

Winfried Kamp

Christian Pacha

Heinz Söldner

Dominik Lorenz

Joerg Berthold

Joel Hatsch

Ralf Arnold

Michael Scheppler

Jörg Gliese

Karl J Zapf

Eva Lackerschmid

Volker Schöber

Thomas Künemund

Ronald Künemund

Matthias Heinitz

Noel Hatsch

Michel D'Argouges

A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Pulsed static flip-flop

A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.

Circuit arrangement, electronic mechanism, electrical turn out and procedures for the operation of one circuit arrangement

An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone

A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.

Frequency synthesizer and method

A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Time delay circuit and time to digital converter

A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.

Parity checking circuit for continuous checking of the parity of a memory cell

In order to test digital modules with functional elements, these are divided into test units () which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (), and the test responses resulting from this are evaluated at the outputs of the test unit (). The effect is then encountered that changes at each of the inputs of a test unit () do not all affect a particular output of this test unit (). For every output of the test unit (), it is possible to define a cone () whose apex is formed by the particular output of the test unit () and whose base comprises the inputs of the test unit () where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit () is constructed of sub-patterns, whose length is in particular &#x2266; the number of inputs of the test unit () that are contained in the base of a cone (). Owing to their shorter length, all possible combinations can be used for selecting the sub-patterns, so that a comprehensive function test of the test unit () can be carried out rapidly and with little outlay. In a digital module, this test function may in particular be implemented by a self-test unit () which can switch over the rest of the digital module into a test mode, generates the test patterns on the basis of sub-patterns, loads them into a test-pattern output register () for application to a test unit () and can evaluate the test response subsequently found at the outputs of the test unit () by means of an evaluation unit (), or read it in for evaluation.

System for testing digital components

The present invention provides a CAM (content addressable memory) apparatus having: a first memory device () with a word line input (WL) and at least one storage node () for storing a first bit of a data word; a second memory device () with a word line input (WL) and at least one storage node () for storing a second bit of a data word; and a comparator device () for comparing the first and second stored bits with two precoded comparison bits fed via four inputs () and for driving a hit node () in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.

CAM (content addressable memory) apparatus

A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.

Growing community of inventors

Munich, Germany

Siegmar Köppe