International Business Machines Corporation

Siegfried Neuber

Thomas Schlipf

Arnold Blum

Rolf B Hilgendorf

Johann Hajdu

Udo Wille

Hartmut Ulland

Herbert Chilinski

Fritz Irro

Dietrich W Bock

Dieter Bazlen

Hellmuth R Geng

Jurgen Hass

Rolf Berger

A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

Method and system for the design verification of logic units and use in

In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

Arrangement for micro instruction control

Growing community of inventors

Sindelfingen, Germany

Siegfried Neuber