Infineon Technologies Ag

Infineon Technologies North America Corp.

Siegfried Hart

William G Bliss

Sasan Cyrusian

Stephen James Franck

Elmar Bach

James Wilson Rae

Thomas Blon

Heinz Werker

Michael A Ruegg

Palaksha Setty

Fritz Mistlberger

Ulrich Huewels

Sriharsha Annadore

A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection circuit connected to a digital phase detector and an analog phase detector for avoiding a phase quantization error. The lock detection circuit activates the analog phase detector to run simultaneously with a digital phase detector if the phase error is zero. The activated analog phase detector regulates the output clock signal of the digitally controllable oscillator in a continuously variable manner until the respective clock signal edges of the output clock signal and the reference clock signal are fully synchronous. The lock detection circuit deactivates the analog phase detector and continuously checks and regulates the digital phase detector until the phase error between the output clock signal and the reference clock signal is zero.

Low jitter analog-digital locker loop with lock detection circuit

A method and apparatus for running an analog portion ( ) of a read/write channel ( ) from a highly regulated power supply ( ). The apparatus includes an analog portion ( ), a clock synthesizer ( ), and a highly regulated power supply ( ) connected to the analog portion ( ) and the clock synthesizer ( ). The analog portion ( ) and the clock synthesizer ( ) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply ( ) supplies power that is within the first voltage range to the analog portion ( ) and the clock synthesizer ( ). The method includes generating power that is within the first voltage range using the highly regulated power supply ( ), and supplying the power to the analog portion ( ) and the clock synthesizer ( ).

Efficient analog front end for a read/write channel of a hard disk drive running from a highly regulated power supply

A variable gain amplifier (&ldquo;VGA&rdquo;) having an open loop architecture is disclosed. The VGA includes one or more gain cells coupled in the signal path to amplify a given input signal. The VGA further includes a replica gain cell having a gain servo circuit which amplifies a gain reference signal according to a programmable gain input and equalizes the amplified reference signal to the original unamplified reference signal, continuously generating a gain control input to the signal path gain cells based on the equalization. This gain control input reflects the gain set by the programmable gain input as adjusted for process, temperature and supply voltage variations. The replica gain cell further includes a common mode voltage servo circuit which senses the common mode voltage of the amplified reference signal and equalizes it to a common mode voltage reference, generating a common mode voltage control signal to the signal path gain cells to regulate their common mode voltage. This regulation of the common mode voltage of the signal path gain cells is compensated for process, temperature and supply voltage variations.

Open loop variable gain amplifier using replica gain cell

Automatic gain control circuit for setting the gain of a signal amplifier having a peak value detector for measuring signal amplitudes of the analogue signal which is amplified by the signal amplifier, a comparator circuit which compares the measured signal amplitudes with an upper threshold value and a lower threshold value and generates digital range display data items which in each case indicate whether the measured signal amplitudes lie below the lower threshold value, between the two threshold values or above the upper threshold value, and having a digital control circuit which incrementally changes the gain of the signal amplifier as a function of the generated digital range display data until the digital range display data indicate that the measured signal amplitudes between the two threshold values lie in a lock-in amplitude range.

Method and circuit for automatic gain control of a signal amplifier

A differential line driver having integrated output termination resistors is disclosed. The termination resistors are a combination of a controlled transistor and a low precision resistor. The transistor calibrates-out the imprecision of the resistor based on a precise electrical reference. In a preferred embodiment the transistor is a CMOS transistor and the resistor is a CMOS resistor. The combination of a CMOS transistor and CMOS resistor features higher linearity and precision than a CMOS transistor alone due to the smaller effective drain-source voltage across the CMOS transistor. Moreover, the present invention discloses independent programmability of the integrated output termination resistor, the output common mode voltage, and the output amplitude. The value of the output termination resistor(s), the value of the output common mode voltage, and the value of the output amplitude are controlled independently and are continuously maintained with respect to a precise electrical reference. As a result, the value of the output termination resistance, the value of the output common mode voltage, and the value of the output amplitude are insensitive to manufacturing process tolerances and variations in temperature and supply voltage.

Output controlled line driver with programmable common mode control

Growing community of inventors

Santa Cruz, CA, United States of America

Siegfried Hart