Ant Nachrichtentechnik Gmbh

Siegfried Brunle

Wolfgang Ehrlich

Rainer Nawrocki

Klaus Eberspacher

A circuit arrangement for imaging a useful digital signal from a frame of a first digital signal having a first bit rate into a frame of a second digital signal having a second bit rate, where the useful digital signal had been written into a first elastic memory and then read out of the first elastic memory in the frame of the first digital signal using a pulse stuffing technique, and with the frame of the first digital signal containing data representing the average fill level of the first elastic memory. The arrangement includes a second elastic memory, a frame detector for detecting the frame of the first signal and controlling activation of write-in of the useful digital signal from the frame of the first digital signal to the second elastic memory, and a frame generator which generates the frame of the second digital signal and controls activation of stuffing and of read-out of the useful digital signal from the second elastic memory into the frame of the second digital signal. An integrator determines the average fill level of the second elastic memory and a subtracter determines the difference between the average fill levels of the first and second elastic memories. This digital difference is fed to a digital control circuit, which includes a digital filter and a pulse density modulator that makes a stuffing decision as a function of the output of the digital filter. Each stuffing decision is input to the frame generator.

Arrangement for imaging a useful signal from the frame of a first

A method of recovering an original digital signal, after pulse stuffing, with reduced waiting time jitter. The original digital signal is written into a first elastic memory in a synchronizer. A pulse stuffed output of the synchronizer is transmitted to a desynchronizer where bits of the original signal are written into second elastic memory. Average values of fill levels of elastic memories in a synchronizer and in a desynchronizer are determined. The average value determined in the synchronizer is transmitted to the desynchronizer where a comparison of the respective average values is made in a comparator. A clock signal generating circuit in a phase locked loop is controlled by an output signal of the comparator so as to generate a clock signal. The signal bits written into the second elastic memory are read out of the second elastic memory at the rate of the generated clock signal.

Method of reducing waiting time jitter

A method of expanding a regular three-stage switching array. Original switching blocks of the first and third stages having a smaller number of crosspoints are enlarged to switching blocks having a larger number of crosspoints, by combining the original switching blocks. In addition, the three stages are expanded by adding additional switching blocks. After the enlarged blocks are formed, at least one additional block is added to the second stage, and some of the connection paths between the enlarged blocks and the blocks of the second stage are rerouted to the additional blocks. The rerouting is performed for the original blocks of the second stage one at a time. In order to avoid disruption of operations during the expansion, while the rerouting is being performed for any particular original block of the second stage, the connections between that original block and the enlarged blocks which would otherwise be established, are switched through redundant connection paths in the second stage. When the rerouting for the original block is complete, these connections are switched back to the connection paths of the original and added blocks of the second stage. After repeating the above for all original blocks of the second stage, the outputs of additional blocks of the first stage and the inputs of additional blocks of the third stage are respectively connected with the inputs and outputs that are still free in the now existing original and additional blocks of the second stage.

Method of expanding a three-stage regular switching array

A three-stage non-blocking switching array having twice the number of inputs and outputs for its sub-arrays of its input and output stages as the number of lines to be switched, and having one more sub-array in its intermediate stage than the minumum required to form a non-blocking switching array. The additional or redundant inputs and outputs are connected with the non-redundant inputs and outputs such that the redundant inputs are each individually connected with a non-redundant input of a respective other sub-array of the same respective stage. This construction maintains the non-blocking characteristic of the switching array even if one of the sub-arrays fails since, in such use, redundant substitute paths are available.

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Esslingen, Germany

Siegfried Brunle