Palo Alto Networks, Inc.

Apple Inc.

Auradine, Inc.

Sidong Li

Jason Rupert Redgrave

Jerome Francis Duluk, Jr

Joseph P Bratt

Emerson S Fang

Richard E Hessel

Sushma Shrikant Trivedi

Vaughn Todd Arnold

Lei Chang

Jack Benkual

Hengwei Hsu

Stephen L Dodgen

Matthew N Papakipos

Subramani Ganesh

Sam Ng

Nathan D Tuck

George Cuan

Zhaoyu Gong

Thomas Y Ho

Tuan Anh Nguyen

Abbas Rashid

Shun Wai Go

Abraham Mammen

Bo Hong

Saptadeep Pal

Joseph P Grass

Lindy Fung

Albert Suan-Wei Tsay

William Alan Roberson

Patrick Xu

Gyanesh Saharia

Savitha Raghunath

De Vu

Minglei Wang

David Carlson

Raju Rakha

Matthew Tomei

Thomas Y Yo

An electronic system for calculating and mining digital currency using circuits optimized for efficient utilization of hash engine circuitry by determining an effective hash clock operational frequency for one or more hash engines in the system. The hash engines can be evaluated to determine a maximum operational frequency for a given error threshold. The hash engines can also be partitioned into one or more hash engine groups to allow different groups to operate at different overclocked frequencies.

Overclocking system for digital currency mining and method of operation

A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input.

End-to-end hardware acceleration for ZKP from witness generation to proof generation

Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lookup using a lookup key, wherein the lookup key comprises a current state and the input value; and determining a next state based on the lookup key.

Reduction and acceleration of a deterministic finite automaton

A network security device includes a network flow statistics processing engine to process network flow information related to network flows. The network flow statistics processing engine includes a first processing stage performing per-flow information aggregation and a second processing stage performing per-destination system component information aggregation, with each processing stage implementing a threshold-based data export scheme and a timer-based data export scheme. In this manner, up-to-date flow information is available to peer system components regardless of the varying flow rates of the network flow.

Network device implementing two-stage flow information aggregation

A security device performing flow classification and storing flow information in a flow table includes a flow engine generating a flow key identifying a flow to which a received data packet belongs, the flow engine applying a hash function to the flow key to generate a flow hash value and an entry hash value being orthogonal to each other. The security device includes a hash map and a flow data table. The hash map table is indexed by the flow hash value and an entry index value is derived from the entry hash value. The flow data table is indexed by the flow hash value and the entry index value to return at least a retrieved flow key from a flow record of an indexed entry.

Security device implementing flow lookup scheme for improved performance

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Graphics processor with deferred shading

Growing community of inventors

San Jose, CA, United States of America

Sidong Li